Adaptec, Inc.

Uday N Devanagundy

Stillman F Gates

Taikhim Henry Tan

An integrated circuit includes a monitor port, several circuit modules, and a selection circuit that selects which of the circuit modules drives internal signal through the monitor port. A debugging process can observe the internal signals at the monitor port to identify problems in the integrated circuit. In one embodiment, the selection circuit includes a trace bus that runs serially from the monitor port to each circuit module. Each module has tri-state buffers that connect the module to the trace bus. Alternatively, the selection circuit includes a multiplexer with input ports coupled to the modules. A trace select register controls which module drives the monitor port, and control registers or the current operation of each module select which set of internal signals the module applies to the tri-state buffers. Any of large number of internal signals can be selected and observed by programming the trace select register and the configuration registers for the modules. In one embodiment, the integrated circuit is a host adapter that includes modules operating in different clock domains.

Monitor port with selectable trace support

A memory architecture for a circuit such as a host adapter provides sections of memory used for different types of information and programmable sizes for the sections. Thus, the circuit can adapt memory configurations for different applications. Each section is divided into pages, and for each section, the circuit has a range of internal addresses that map to a current page in the section. Additionally, the circuit has several operating modes and several register sets. Each mode has a set of functions that the circuit performs and a register set that the circuit can access while operating in the mode. Currently accessible pages in the memory are selected according to the operating mode. In particular, the register sets include registers for pointers that identify pages currently accessible. When the circuit switches modes, the accessible register set changes, and changing the register set changes the pointers and which pages are accessible. Generally, the accessible register set and memory pages are selected according to the function of the mode. Accordingly, the internal address space for accessing registers and memory can be minimized, since only the registers and pages needed for the functions of a mode are accessible while the circuit operates in the mode.

Host adapter having a plurality of register sets and corresponding operating nodes

An integrated circuit such as a host adapter for connection to a system bus of a host computer includes a memory interface for a local memory including a serial memory such as an SEEPROM. The memory interface is capable of unsupervised multi-bit transfers between the serial memory and a data register in the memory interface. The host computer to access the serial memory starts the memory interface on a multi-bit access (i.e., read, write, or erase), checks a busy bit in the memory interface to determine when the access is complete, and accesses the data register. Thus, the host computer is decoupled from bit-by-bit management of transfers, and the integrated circuit or a bus device incorporating the integrated circuit requires less software overhead for use of serial memory. The memory interface further includes protection circuitry that prevents writing or erasing of a portion of the memory that a flag designates as protected. The flag is in a register that does not permit changes unless the host adapter is in a state such as corresponding to a target abort exists. Accordingly, the host can write or erase protected memory by causing a target abort, changing the flag to unprotect the memory, and then changing the memory. Since the state is unlikely to exist when a software might unintentionally access the flag, unintended changes to the protected memory are unlikely.

Decoupled serial memory access with passkey protected memory areas

A circuit such as a host adapter includes a timer capable of detecting time-outs for multiple pending commands. The timer includes a single free-running counter, a first storage for start counts, a second storage for time-out values, a subtractor, and a comparator. The start counts are counts from the counter that are saved when issuing an associated command. The time-out values indicate the lengths of different types of time-out periods. To check whether a command timed out, a start count associated with the command is selected from the first storage, and the subtractor determines a difference between a current count in the counter and the selected start count. The difference is then compared to a time-out value that is selected from the second storage according to the type of time-out. The command timed out if the difference is greater than the selected time-out value. In one embodiment, the second storage includes count registers for time-out values, a multiplexer, and select register that provides a select signal to the multiplexer. The select register contains a value associated with the command, and the number of count registers matches the number of types of time-outs.

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Hayward, CA, United States of America

Uday N Devanagundy