Samsung Electronics Co., Ltd.

U-in Chung

Ho-jung Kim

Jai-kwang Shin

Hyun-sik Choi

Jong-Ho Lee

Chang-jung Kim

Si-Young Choi

I-hun Song

Tai-Su Park

Eui-Joon Yoon

Young-sun Kim

Ki-Nam Kim

Sun-il Kim

Hong-Jae Shin

In-kyeong Yoo

Jong-seob Kim

Kyung-Hyun Kim

Sung-chul Lee

Jae-joon Oh

Ki-ha Hong

Hyun-jong Chung

Seung-eon Ahn

Kee-won Kim

In-jun Hwang

Kwang-seok Kim

Bum-Soo Kim

Sang-Hun Jeon

Hyuk-Soon Choi

Beom-jun Jin

Ung-hwan Pi

Yoo-Cheol Shin

Eun-ae Chung

Ji-hyun Choi

Ki-hyun Hwang

Chang-Ki Hong

Jung-Hwan Oh

Hee-Seok Kim

Seok-woo Nam

Won-sik Shin

Hyo-jung Kim

Byung-keun Hwang

Kyu-Chan Park

A logic device includes: a function block and a configuration block. The function block is configurable to perform operations associated with a plurality of operation modes. The configuration block is configured to configure the function block to perform an operation associated with any one of the plurality of operation modes. The logic device also includes a controller configured to control the configuration block so that the function block is configured to perform the operation.

Logic devices, digital filters and video codecs including logic devices, and methods of controlling logic devices

A power management chip and a power management device including the power management chip. The power management chip includes at least one power switch and a driver unit for generating a driving signal for driving the at least one power switch, the driver unit including one or more circuit units formed on a same substrate as the at least one power switch.

Power management chips and power management devices including the same

A color optical pen includes a tip unit, a pen body unit attached to the tip unit; a pressure sensor that is disposed in the tip unit and configured to sense at least contact between a display unit of a terminal device and the tip unit; a light source that is disposed in the pen body unit and is configured to output light through the tip unit, if the pressure sensor senses the contact; a color selection switch that is disposed on the pen body, the color selection switch configured to select a color in response to operation by a user; and a driver configured to drive the light source at a frequency or pattern based on operation of the color selection switch.

Color optical pen for electronic panel

A high side gate driver, a switching chip, and a power device, which respectively include a protection device, are provided. The high side gate driver includes a first terminal configured to receive a first low level driving power supply that is provided to turn off the high side normally-on switch; a first switching device connected to the first terminal; and a protection device connected in series between the first switching device and a gate of the high side normally-on switch, the protection device configured to absorb a majority of a voltage applied to a gate of the high side normally-on switch. The power device includes the high side gate driver. In addition, the switching chip includes a high side normally-on switch, an additional normally-on switch, and a low side normally-on switch, which have a same structure.

High side gate driver, switching chip, and power device

A logic device includes first and second logic blocks and a connection block. Each of the first and second logic blocks configured to perform at least one function, the first logic blocks connected to first connection lines and the second logic blocks connected to second connection lines. The connection block electrically connected to the first and second logic blocks via the first connection lines and the second connection lines, respectively. The connection block including connection cells configured to select one of multiple connection configurations between the first connection lines and the second connection lines based on a desired function.

Logic device and operating method thereof

Image sensors and methods of operating the same. An image sensor includes a pixel array including a plurality of pixels. Each of the plurality of pixels includes a photo sensor, the voltage-current characteristics of which vary according to energy of incident light, and that generates a sense current determined by the energy of the incident light; a reset unit that is activated to generate a reference current, according to a reset signal for resetting at least one of the plurality of pixels; and a conversion unit that converts the sense current and the reference current into a sense voltage and a reference voltage, respectively.

Image sensors having variable voltage-current characteristics and methods of operating the same

A power module including a power device and a periphery circuit configured to suppress a leakage current in the power device. The periphery circuit includes a leakage current detection circuit configured to detect a leakage current from the power device and control operation of the power device based on a result of the detection. The leakage current detection circuit including an input terminal connected to the power device, a plurality of NMOS transistors, a plurality of PMOS transistors connected to the plurality of NMOS transistors, and a comparator.

Power module including leakage current protection circuit

A storage node of a magnetic memory device includes: a lower magnetic layer, a tunnel barrier layer formed on the lower magnetic layer, and a free magnetic layer formed on the tunnel barrier. The free magnetic layer has a magnetization direction that is switchable in response to a spin current. The free magnetic layer has a cap structure surrounding at least one material layer on which the free magnetic layer is formed.

Storage nodes, magnetic memory devices, and methods of manufacturing the same

A graphene transistor includes: a gate electrode on a substrate; a gate insulating layer on the gate electrode; a graphene channel on the gate insulating layer; a source electrode and a drain electrode on the graphene channel, the source and drain electrode being separate from each other; and a cover that covers upper surfaces of the source electrode and the drain electrode and forms an air gap above the graphene channel between the source electrode and the drain electrode.

Graphene transistor having air gap, hybrid transistor having the same, and methods of fabricating the same

A semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a voltage generator configured to generate a test voltage, a graphene transistor configured to receive a gate-source voltage based on the test voltage, and a detector configured to detect whether the gate-source voltage is a Dirac voltage of the graphene transistor, and output a feedback signal applied to the voltage generator indicating whether the gate-source voltage is the Dirac voltage.

Semiconductor device and method of operating the semiconductor device

A method of manufacturing a High Electron Mobility Transistor (HEMT) may include forming first and second material layers having different lattice constants on a substrate, forming a source, a drain, and a gate on the second material layer, and changing the second material layer between the gate and the drain into a different material layer, or changing a thickness of the second material layer, or forming a p-type semiconductor layer on the second material layer. The change in the second material layer may occur in an entire region of the second material layer between the gate and the drain, or only in a partial region of the second material layer adjacent to the gate. The p-type semiconductor layer may be formed on an entire top surface of the second material layer between the gate and the drain, or only on a partial region of the top surface adjacent to the gate.

Method of manufacturing high electron mobility transistor

A method of forming a field effect transistor includes forming a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and forming an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The method may also include forming a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, forming a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and forming a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction.

Methods of fabricating vertical channel field effect transistors having insulating layers thereon

A capacitor of a semiconductor device includes a cylinder type capacitor lower electrode, a dielectric layer, and an upper electrode. The upper electrode includes a metallic layer on the dielectric layer and a doped polySiGelayer stacked on the metallic layer. Methods of forming these capacitors also are provided.

Methods of forming capacitors of semiconductor devices including silicon-germanium and metallic electrodes

A field effect transistor can include a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The transistor can also include a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction. Related methods are also disclosed.

Vertical channel field effect transistors having insulating layers thereon

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Seoul, South Korea

U-in Chung