University of Macau

U-Fat Chio

Rui Paulo Da Silva Martins

Seng-Pan U

Sai-Weng Sin

Yan Zhu

Franco Maloberti

Chi-Hang Chan

He-Gong Wei

Chi-Seng Lam

Man-Chung Wong

Wai-Hei Choi

Ning-Yi Dai

Yajie Wu

Chi-Kong Wong

Yan-Zheng Yang

Li Ding

A mixed signal controller for a power quality compensator includes an analog circuit, an analog-to-digital converter (ADC), and a digital circuit. The analog circuit amplifies an input signal from the power quality compensator by a gain factor and outputs an analog signal, which is converted to a digital signal by the ADC. The digital circuit receives the digital signal, calculates the reference compensating current of each phase and then generates a trigger signal via hysteresis PWM to the power quality compensator. The digital circuit includes an evaluation circuit that calculates a value of the system total harmonic distortion after the power quality compensator compensates power and adjusts the gain factor when the value of the system total harmonic distortion reaches a predetermined threshold.

Mixed signal controller

A comparator is provided and the comparator includes a comparing input unit and a latching unit. Wherein, the comparing input unit has a first input receiving a first comparing signal and has a second input receiving a second comparing signal. The comparing input unit drives a first intermediate node signal at a first intermediate node depending on the first comparing signal according to a first strobe signal, and the comparing input unit drives a second intermediate node signal at a second intermediate node depending on the second comparing signal according to the first strobe signal. The latching unit determines a comparing result according to at least one of the first intermediate node signal and the second intermediate node signal. In addition, the latching unit latches the comparing result according to a second strobe signal.

Comparator and calibration thereof

A novel analog-to-digital converter (ADC) system using a two-step conversion is disclosed. The ADC system is capable of achieving high sampling rate, low power consumption and low complexity. The new proposed ADC is formed by cascading a flash ADC having high sampling rate and low resolution with a successive approximation (SA) ADC having low power consumption and low sampling rate.

Cascade analog-to-digital converting system

A delay generator comprises: a current source for supplying a current; a first delay portion, connected to the current source, comprising at least a plurality of inverters and a first capacitor having a first capacitance; and a second delay portion, connected to the current source, comprising at least a plurality of inverters and a second capacitor having a second capacitance, wherein the first capacitance is the same as the second capacitance, wherein the first delay portion generates a first delay by discharging of the first capacitor, wherein the second delay portion generates a second delay by charging of the second capacitor, and wherein the total delay generated by the delay generator is obtained by summation of the first delay and the second delay.

Delay generator

An analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design.

Time-interleaved pipelined-SAR analog to digital converter with low power consumption

The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising: an n-bits SAR control logic, a p-type capacitor network including a DACarray and a sampling capacitor C, an n-type capacitor network including a DACarray and a sampling capacitor C; and a comparator for comparing outputs from the p-type capacitor network and the n-type capacitor network, wherein a power supply and ground are directly connected to the p-type capacitor network and the n-type capacitor network without using reference voltages produced by a reference voltage generator. The n-bits SAR control logic comprises n shift registers, n bit registers, and a switching logic. The comparator comprises a first pre-amplifier, a second pre-amplifier and a dynamic latch. Alternative, the comparator comprises a four-input pre-amplifier and a dynamic latch.

Growing community of inventors

Macau, China

U-Fat Chio