Unimicron Technology Corporation

Harvatek Corporation

Express Packaging Systems, Inc.

Tzyy Jang Tseng

Bily Wang

Shao-Chien Lee

Chang-Ming Lee

John H Lau

Alen Ke

Chen-Hua Cheng

A method for fabricating an electrical interconnect structure is adapted for a circuit board manufacturing process. The circuit board comprises a conductive substrate, which comprises a first conductive layer and a bump conductive layer. The bump conductive layer is patterned to form at least one bump over the first conductive layer. Then, a dielectric layer is formed over the first conductive layer and the bump. A second conductive layer is formed over the dielectric layer. At least one blind hole is formed in the second conductive layer and the dielectric layer, passing through the second conductive layer and the dielectric layer to expose the top surface of the bump. A conductive material is filled in the blind hole, and the conductive material in the blind hole and the bump constitute a conductive post.

Method for fabricating electrical interconnect structure

A light emitting diode chip or chips array mounted on a substrate is surrounded by one or more side walls. The wall has an uneven reflecting surface to diverge the light emitted from the LED chip or chip array. The wall may have a triangular cross-section so that the emitted light diverges in all directions. When three double-sided reflecting walls surround three LED panels, the reflected light becomes omnidirectional hemispherically and can be used in a light bulb.

LED light source with reflecting side wall

The present invention discloses a new semiconductor ball grid array package for integrated circuits which have input and output counts higher than 250. The speed and performance characteristics of the semiconductor device contained in the package assembly are optimized while the packaging structure is simplified by utilizing only one dielectric layer and regular printed circuit board fabrication process. The complexities and higher cost for production of a multiple layer substrate for high-density interconnection configuration are thus resolved. The improved package assembly is achieved by implementing a segmented ring on one side of a substrate and a split plane on the other side thus forming a single layer substrate structure. The edges of the substrate are coated with metal layer to provide interlayer connections. The package assembly applies a cavity down configuration with an integrated heat spreader attached. The IC wire bonds within the cavity are sealed with an organic encapsulant. In addition to the benefits of high performance low cost, the improved circuit structure and package layout provide flexibility allowing higher degree of freedom for selecting the location and number of input and output signal lines and connections to the ground and power planes from the semiconductor device.

Heat spreader with a placement recess and bottom saw-teeth for

Growing community of inventors

Hsinchu, Taiwan

Tzyy Jang Tseng