Spansion Llc.

Sun Microsystems, Inc.

Oracle America, Inc.

Trimedia Technologies, Inc.

Tzungren A Tzeng

Kevin B Normoyle

Choon Ping Chng

Rajasekhar Cherabuddi

Michael A Csoppenszky

Jui-Cheng Su

Jaybharat Boddu

Choon-Ping Chng

Alex S Han

Eino Jacobs

Michael L Ott

Mahmudul Hassan

A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.

Partial allocate paging mechanism using a controller and a buffer

A method of operating a memory system is provided. The method includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.

Mitigate flash write latency and bandwidth limitation by preferentially storing frequently written sectors in cache memory during a databurst

Mitigate flash write latency and bandwidth limitation with a sector-based write activity log

A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.

Flash memory usability enhancements in main memory application

Operating system based DRAM/FLASH management scheme

Hardware based wear leveling mechanism for flash memory using a free list

Memory resource management for a flash aware kernel

Flash memory and operating system kernel

Wear leveling mechanism using a DRAM buffer

Mitigation of flash memory latency and bandwidth limitations via a write activity log and buffer

Expansion slots for flash memory based random access memory subsystem

A data communications system is disclosed. The data communications system comprises two clock domains. Each of the clock domains are coupled to receive a source clock signal. The first clock domain includes a first clock signal and the second clock domain includes a second clock signal, each of the first clock signal and the second clock signal are derived from the source clock signal. The first clock signal has a frequency which is different from that of the second clock signal. The system includes circuitry configured to generate a pulse indicative of when data transferred between the first clock domain and the second clock domain may be latched. Data is only latched when the pulse is asserted and on a given edge of the first clock signal, and the circuitry is configured to generate the pulse such that the given edge occurs at approximately a position corresponding to a middle of a period of the second clock signal.

Skew tolerant communication between ratioed synchronous clocks

A method of executing a fused instruction is disclosed. The method begins by performing several actions, which may be performed serially or in parallel. These include performing a floating point multiplication of a first floating point number by a second floating point number and normalizing a third floating point number. The floating point multiplication of the first and second floating point numbers generates a first result, while the normalization generates a second result. The first result is then added to the second result, generating an unnormalized result. A determination is also made as to whether a large exponent difference exists between the first result and the second result. If a large exponent difference exists between the first result and the second result, a large exponent difference normalization is performed on the unnormalized result. Otherwise, a small exponent difference normalization is performed on the unnormalized result.

Method and apparatus for performing fused instructions by determining exponent differences

Disclosed herein is an apparatus and method for determining if a first number is greater than or equal to a second number. By analyzing nibbles of a multi-bit number in parallel to determine for each nibble if the nibbles are unequal and if a first nibble is greater than a second nibble and thereafter logically determining which of the highest order nibbles, if any, are unequal to discover whether the first number is greater than the second number, or determining that all nibble pairs are equal and thus concluding that both numbers are equal. A digital logic circuit is preferably employed for such analysis.

Parallel greater than analysis method and apparatus

Growing community of inventors

San Jose, CA, United States of America

Tzungren A Tzeng