United Microelectronics Corp.

Tzu-Yun Chang

Hsueh-Chun Hsiao

Ko-Chi Chen

Yi-Ning Peng

Chung-Tse Chen

Wen-Hsin Hsu

Chuan-Fu Wang

Cheng-Tung Huang

Shih-Yin Hsiao

Ping-Chia Shih

Kuan-Yang Liao

Ching-Chung Yang

Bang-Chiang Lan

Chen-Hua Tsai

Chi-Cheng Huang

Wei-Tsun Shiau

Cheng-Tzung Tsai

Yi-Cheng Liu

Yu-Huang Yeh

Po-Wei Liu

Tse-Min Chao

Wen-Chi Chen

Yi Ting Hung

Hsuan-Chun Tseng

An electrically erasable programmable read only memory (EEPROM) includes a substrate, isolation structures, a row of erase gate and a row of floating gates. The isolation structures are defined in the substrate to extend in a first direction. The row of erase gate having a wave shape is disposed across the substrate. The row of floating gates having staggered islands is disposed parallel to the row of erase gate. A method of forming said electrically erasable programmable read only memory (EEPROM) is also provided.

Semiconductor structure with wave shaped erase gate and forming method thereof

A forming operation method of a resistive random access memory is provided. The method includes the following steps. A positive pulse and a negative pulse are sequentially applied, by a bit line/source line driver, to multiple resistive random access memory cells in a direction form a farthest location to a nearest location based on the bit line/source line driver through a bit line and a source line to break down a dielectric film of each of the resistive random access memory cells and generate a conductive filament of each of the resistive random access memory cells.

Forming operation method of resistive random access memory

An array of programmable memory includes a first floating gate and a second floating gate disposed on a substrate along a first direction, two spacers disposed between and parallel to the first floating gate and the second floating gate, a first word line sandwiched by one of the spacers and the adjacent first floating gate, and a second word line sandwiched by the other one of the spacers and the adjacent second floating gate, and two first spacers disposed on the substrate, wherein one of the first spacer is disposed between the first word line and the first floating gate, and another spacer is disposed between the second word line and the second floating gate, wherein each spacer has substantially the same shape as each first spacer.

Programmable memory and forming method thereof

An array of electrically erasable programmable read only memory (EEPROM) includes a first row of floating gate, a second row of floating gate, two spacers, a first row of word line and a second row of word line. The first row of floating gate and the second row of floating gate are disposed on a substrate along a first direction. The two spacers are disposed between and parallel to the first row of floating gate and the second row of floating gate. The first row of word line is sandwiched by one of the spacers and the adjacent first row of floating gate, and the second row of word line is sandwiched by the other one of the spacers and the adjacent second row of floating gate. The present invention also provides a method of forming said array of electrically erasable programmable read only memory (EEPROM).

Method for forming programmable memory

A semiconductor memory device includes a substrate, a dielectric layer on the substrate, and a contact plug in the dielectric layer. An upper portion of the contact plug protrudes from a top surface of the dielectric layer. The upper portion of the contact plug acts as a first electrode. A buffer layer is disposed on the dielectric layer and beside the upper portion of the contact plug. A resistive-switching layer is disposed beside the buffer layer. A second electrode is disposed beside the resistive-switching layer.

Semiconductor memory device and fabrication method thereof

A method for fabricating memory device is provided. The method includes forming a transistor on a substrate. Further, a contact structure is formed on a source/drain region of the transistor. A conductive layer is formed on the contact structure. Four memory structures are formed on the conductive layer to form a quadrilateral structure.

Method for fabricating memory device

A structure of memory device is provided. The structure of memory device includes a transistor formed on a substrate. A contact structure is disposed on a source/drain region of the transistor. A conductive layer is disposed on the contact structure. Four memory structures is disposed on the conductive layer to form a quadrilateral structure.

Structure of memory device and fabrication method thereof

A memory structure including a substrate, a first gate structure, a second gate structure, a first spacer, a second spacer, and a third spacer is provided. The first gate structure includes a first gate and a charge storage layer. The charge storage layer is disposed between the first gate and the substrate. The second gate structure is disposed on the substrate. The second gate structure includes a second gate. A height of the first gate is higher than a height of the second gate. The first spacer and the second spacer are respectively disposed on one sidewall and the other sidewall of the first gate structure. The first spacer is located between the first gate structure and the second gate structure. The third spacer is disposed on a sidewall of the first spacer and covers a portion of a top surface of the second gate.

Memory structure and manufacturing method thereof

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a plurality of isolation structures, a charge storage layer, and a conductive layer. The substrate has a memory region and a logic region. The substrate in the memory region has a plurality of semiconductor fins. The isolation structures are disposed in the substrate to isolate the semiconductor fins. The semiconductor fins are protruded beyond the isolation structures. The charge storage layer covers the semiconductor fins. The conductive layer is disposed across the semiconductor fins and the isolation structures such that the charge storage layer is disposed between the conductive layer and the semiconductor fins.

Semiconductor device and manufacturing method thereof

A semiconductor structure includes a memory unit structure. The memory unit structure includes a transistor, a first electrode, two second electrode, and two resistive random access memory (RRAM) elements. The first electrode and the two second electrodes are disposed in a horizontal plane. The first electrode is disposed between the two second electrodes. The first electrode and the two second electrodes are disposed in parallel. The first electrode is coupled to a source region of the transistor. One of the two RRAM elements is disposed between the first electrode and one of the two second electrodes. The other one of the two RRAM elements is disposed between the first electrode and the other one of the two second electrodes.

Resistive memory and method for manufacturing the same

The present invention provides a test key array including a lower conductive pattern, and the lower conductive pattern includes a plurality of first L-shaped traces parallel to each other, an upper conductive pattern, where the upper conductive pattern includes a plurality of second L-shaped traces parallel to each other, the lower conductive pattern crosses to the upper conductive pattern, and a plurality of cross regions are defined between the lower conductive pattern and the upper conductive pattern, and a plurality of conductive plugs, disposed on parts of the cross regions, electrically connecting to the lower conductive pattern and the upper conductive pattern.

Test key array

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate; a first and a second ion implantation regions of a first conductive type; a source and a drain diffusion regions formed in the first and the second ion implantation regions respectively; a channel diffusion region formed between the first and the second ion implantation regions; a gate layer disposed above the channel diffusion region and located between the source and the drain diffusion regions; and a third ion implantation region of a second conductive type formed in the gate layer, which extends in a first direction. The third ion implantation region is located above and covers two side portions of the channel diffusion region, the two side portions are adjacent to two edges, extending in a second direction perpendicular to the first direction, of the channel diffusion region.

Semiconductor structure and manufacturing method thereof

The invention is directed to a method for forming a metal-oxide semiconductor field effect transistor. The method comprises steps of providing a substrate having a gate structure formed thereon, wherein a plurality of isolation structures are located in the substrate adjacent to both sides of the gate structure and then forming a first spacer on the sidewall of the gate structure. A portion of the substrate between the first spacer and the isolation structures is removed to form a recession and a source/drain layer is deposited in the recession, wherein the top surface of the source/drain layer is higher than the top surfaces of the isolation structures. A second spacer is formed on the isolation structures and at the sidewall of the source/drain layer and a metal silicide layer is formed on the source/drain layer.

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Hsinchu County, Taiwan

Tzu-Yun Chang