Taiwan Semiconductor Manufacturing Comp. Ltd.

Tzu-Yu Wang

Shin-Puu Jeng

Shang-Yun Hou

Wei-Cheng Wu

Hsien-Pin Hu

Chen-Hua Douglas Yu

Tzu-Wei Chiu

Tzuan-Horng Liu

Hsien-Wei Chen

An-Jhih Su

Kewei Zuo

Chih-Wei Lai

Chi-Chun Hsieh

Wen-Chih Chiou

Kuo-Ching Hsu

Henry Lo

Chien Rhone Wang

Hung-An Teng

Jung Cheng Ko

Li-Han Hsu

Jean Wang

Liwei Lin

Francis Ko

Chun-Yi Liu

Meng-Han Lee

Kuan Teng Lo

An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.

Interposer test structures and methods

A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and a second bump on a second semiconductor component. The first bump has a first non-flat portion (e.g., a convex projection) and the second bump has a second non-flat portion (e.g., a concave recess). The bump structure also includes a solder joint formed between the first and second non-flat portions to electrically couple the semiconductor components.

Bump structure for yield improvement

A first embodiment is a method for semiconductor process control comprising clustering processing tools of a processing stage into a tool cluster based on processing data and forming a prediction model for processing a semiconductor wafer based on the tool cluster. A second embodiment is a method for semiconductor process control comprising providing cluster routes between first stage tool clusters and second stage tool clusters, assigning a comparative optimization ranking to each cluster route, and scheduling processing of wafers. The comparative optimization ranking identifies comparatively which cluster routes provide for high wafer processing uniformity. Further, wafers that require high wafer processing uniformity are scheduled to be processed along one cluster route that has a high comparative optimization ranking that identifies the one cluster route to have a highest wafer processing uniformity, and wafers that do not require high wafer processing uniformity are scheduled to be processed along another cluster route.

Clustering for prediction models in process control and for optimal dispatching

Semiconductor device design methods and conductive bump pattern enhancement methods are disclosed. In some embodiments, a method of designing a semiconductor device includes designing a conductive bump pattern design, and implementing a conductive bump pattern enhancement algorithm on the conductive bump pattern design to create an enhanced conductive bump pattern design. A routing pattern is designed based on the enhanced conductive bump pattern design. A design rule checking (DRC) procedure is performed on the routing pattern.

Semiconductor device design methods and conductive bump pattern enhancement methods

A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate.

Cylindrical embedded capacitors

Embodiments of the present invention relate to a method for a near non-adaptive virtual metrology for wafer processing control. In accordance with an embodiment of the present invention, a method for processing control comprises diagnosing a chamber of a processing tool that processes a wafer to identify a key chamber parameter, and controlling the chamber based on the key chamber parameter if the key chamber parameter can be controlled, or compensating a prediction model by changing to a secondary prediction model if the key chamber parameter cannot be sufficiently controlled.

Near non-adaptive virtual metrology and chamber control

A semiconductor device includes a bonding pad on a substrate. The semiconductor device further includes a passivation layer covering a peripheral portion of the bonding pad while exposing a middle portion of the bonding pad. Additionally, the semiconductor device includes a stress buffer layer over the passivation layer where the stress buffer layer exposes a portion of the bonding pad, and where a wall of the stress buffer layer extends, in steps, upwardly from the exposed portion of the bonding pad. Furthermore, the semiconductor device includes an under-bump metallurgy (UBM) layer over the stress buffer layer, where the UBM layer contacts a portion of the bonding pad.

Stress buffer structures in a mounting structure of a semiconductor device

A mounting structure for a semiconductor device is formed to include a stepwise stress buffer layer under a stepwise UBM structure.

Methods of manufacturing stress buffer structures in a mounting structure of a semiconductor device

Growing community of inventors

Taipei, Taiwan

Tzu-Yu Wang