Taiwan Semiconductor Manufacturing Comp. Ltd.

Lianhong Art Co., Ltd.

Industrial Technology Research Institute

Other

Hon Lin Technology Co., Ltd.

Tzu-Yu Lin

Chia-Hui Chen

Yao-Wen Chang

Yen-Ting Chen

Chia-Wen Zhong

Ting-Chun Liu

Hai-Dang Trinh

Hsun-Chung Kuang

Jian-Hong Chen

Bi-Shen Lee

Sheng-Yueh Chang

Cheng-Yuan Tsai

Yen-Liang Lin

Shang-Ho Tsai

Bang-Chein Ho

Hsin-Hung Chou

Jui-Fa Chang

Wei-Han Hsiao

Yu-Heng You

Chiao-Fang Chang

Jih-Nan Tai

Yi-Yang Wei

Hsing-Lien Lin

Chia-Ming Chang

Hung-Chih Chen

Yi Yang Wei

Chao-Hsin Chang

Weir-Torn Jiaang

Che-Hsien Lin

Chih-Chien Hung

Tsing-Tang Song

Chia Hui Chen

Renn-Shyan Yeh

Der-Fang Huang

Tsong-Shin Jean

Chih-Shin Chuang

Ming-Chia Tai

Han-Bin Cheng

Wen-Yuang Tsai

Mao-Ching Fang

Yao-Chanet Chu

Min-Hsiang Kao

Hsiang-Ho Lo

The present disclosure describes a semiconductor device having a ferroelectric memory with improved retention after cycling (RAC) memory window (MW) performance. The semiconductor device includes an interconnect structure on a substrate, a first electrode on the interconnect structure, a ferroelectric layer on the first electrode, and a second electrode on the ferroelectric layer. The first electrode includes a metal nitride conductive material having a nitrogen concentration greater than a metal concentration. The ferroelectric layer includes a ferroelectric material. The second electrode includes the metal nitride conductive material.

Ferroelectric memory device and method of fabricating the same

Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes an interconnect structure overlying a semiconductor substrate and comprising a conductive wire. A passivation structure overlies the interconnect structure. An upper conductive structure overlies the passivation structure and comprises a first conductive layer, a dielectric layer, and a second conductive layer. The first conductive layer is disposed between the dielectric layer and the passivation structure. The second conductive layer extends along a top surface of the dielectric layer and penetrates through the first conductive layer and the passivation structure to the conductive wire.

Integrated chip including an upper conductive structure having multilayer stack to decrease fabrication costs and increase performance

. Various embodiments of the present disclosure are directed towards a ferroelectric random-access memory (FeRAM) cell or some other suitable type of memory cell comprising a bottom-electrode interface structure. The memory cell further comprises a bottom electrode, a switching layer over the bottom electrode, and a top electrode over the switching layer. The bottom-electrode interface structure separates the bottom electrode and the switching layer from each other. Further, the interface structure is dielectric and is configured to block or otherwise resist metal atoms and/or impurities in the bottom electrode from diffusing to the switching layer. By blocking or otherwise resisting such diffusion, leakage current may be decreased. Further, endurance of the memory cell may be increased.

Bottom-electrode interface structure for memory

The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode disposed within a dielectric structure over a substrate. A ferroelectric data storage structure is disposed over the lower electrode and an upper electrode is disposed over the ferroelectric data storage structure. One or more stressed sidewall spacers are arranged on opposing sides of the upper electrode. The ferroelectric data storage structure has an orthorhombic phase concentration that varies from directly below the one or more stressed sidewall spacers to laterally outside of the one or more stressed sidewall spacers.

Spacer film scheme form polarization improvement

In some embodiments, the present disclosure relates to a memory device including a semiconductor substrate, a first electrode disposed over the semiconductor substrate, a ferroelectric layer disposed between the first electrode and the semiconductor substrate, and a first stressor layer separating the first electrode from the ferroelectric layer. The first stressor layer has a coefficient of thermal expansion greater than that of the ferroelectric layer.

Wakeup free approach to improve the ferroelectricity of FeRAM using a stressor layer

Ferroelectric stacks are disclosed herein that can improve retention performance of ferroelectric memory devices. An exemplary ferroelectric stack has a ferroelectric switching layer (FSL) stack disposed between a first electrode and a second electrode. The ferroelectric stack includes a barrier layer disposed between a first FSL and a second FSL, where a first crystalline condition of the barrier layer is different than a second crystalline condition of the first FSL and/or the second FSL. In some embodiments, the first crystalline condition is an amorphous phase, and the second crystalline condition is an orthorhombic phase. In some embodiments, the first FSL and/or the second FSL include a first metal oxide, and the barrier layer includes a second metal oxide. The ferroelectric stack can be a ferroelectric capacitor, a portion of a transistor, and/or connected to a transistor in a ferroelectric memory device to provide data storage in a non-volatile manner.

Ferroelectric memory device and method of manufacturing the same

Spacer film scheme for polarization improvement

Method for forming an upper conductive structure having multilayer stack to decrease fabrication costs and increase performance

Various embodiments of the present disclosure are directed towards a ferroelectric random-access memory (FeRAM) cell or some other suitable type of memory cell comprising a bottom-electrode interface structure. The memory cell further comprises a bottom electrode, a switching layer over the bottom electrode, and a top electrode over the switching layer. The bottom-electrode interface structure separates the bottom electrode and the switching layer from each other. Further, the interface structure is dielectric and is configured to block or otherwise resist metal atoms and/or impurities in the bottom electrode from diffusing to the switching layer. By blocking or otherwise resisting such diffusion, leakage current may be decreased. Further, endurance of the memory cell may be increased.

A method for downlink transmission in a cloud radio access network for a number of users is applied in a central unit. The central unit determines a specific number of remote radio heads (RRHs) as non-serving RRHs based on a predetermined data compression ratio. For each of many pieces of user equipment (UEs), the central unit determines a combination of RRHs which are non-serving in coordinated multi-point transmission (CoMP) from a plurality of RRHs based on the determined specific number, and then performs CoMP downlink transmission based on the combination of RRHs which are non-serving in the CoMP.

Method and apparatus for downlink transmission in a cloud radio access network

A rebounding pivot module includes a mounting shaft, and a bouncing device set including a barrel having one end tooth shaped, a connecting tube mounted in the other end of the barrel, a connection rod connected to the connecting tube, a socket and a first guide block mounted onto the connection rod, the first guide block having one end beveled, a bouncing barrel mounted around the connecting rod, a second guide block supported on an elastic member in the bouncing barrel and defining therein a guide hole and having one end tooth shaped and abutted at the beveled edge of the first guide block, and a lock device fastened to connection rod that is inserted through the second guide block, the elastic member and the through hole of the bouncing barrel to lock the bouncing barrel to the connection rod.

Rebounding pivot module

A dual-shaft hinge device including a base and two rotatable plates connected to two lateral sides of the base. Each of the first rotatable plate and the second rotatable plate have a semicircular portion on which a plurality of teeth are disposed. A first rotatable rod and a second rotatable rod are disposed in the base. First gear teeth are disposed at one end of the first rotatable rod and mesh with the teeth of the first rotatable plate, and second gear teeth are disposed at one end of the second rotatable rod and mesh with the teeth of the second rotatable plate. An even number of gear rods are disposed in the base and mutually meshed with each other. Two lateral plates are connected to the base to position the aforementioned elements to the base.

Hinge device with dual shaft

A synchronous hinge device includes a first base having a first connecting portion and a first assembling portion. The first connecting portion has a first central groove, a first outer groove, a first through hole and a second through hole. A second base has a second connecting portion and a second assembling portion. The second connecting portion has a second central groove, a second outer groove, a third through hole and a fourth through hole. First, second, third, and forth shafts extending through the first, the second, the third, and the fourth through holes, respectively. A first torque element disposed between the first shaft and the third shaft; and a second torque element disposed between second shaft and the fourth shaft, wherein the first torque element has axle sleeves limiting the first distance, and the second torque element has axle sleeves limiting the second distance.

Synchronous hinge device

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Hsinchu, Taiwan

Tzu-Yu Lin