At&t Bell Laboratories

American Telephone & Telegraph Co., At&t Bell Laboratories

American Telephone and Telegraph, Co.

Tzu-Yin Chiu

Gen M Chin

Alexander M Voshchenkov

Te-Yin M Liu

Kwing F Lee

Maureen Y Lau

Mark D Morris

Ronald C Hanson

William T Lynch

Avinoam Kornblit

Joseph Lebowitz

Alexander M Voschenkov

A novel process is disclosed for fabricating semiconductor devices with self-aligned contacts. Characteristic of the resulting structure is a digitated electrode and a contiguous conductive region that contact first semiconductor regions and second semiconductor regions, respectively. The first semiconductor regions and the second semiconductor regions are formed in a semiconductor substrate, with each second semiconductor region underlying a finger of the digitated electrode. Advantageously, by forming a contiguous conductive region over the first semiconductor regions located between the fingers of the digitated electrode, it is not only possible to contact second semiconductor regions with a common electrode, but also to self-align the common electrode with the digitated electrode. Ohmic shorting between the digitated electrode and the contiguous conductive region is prevented by interposing an insulating region therebetween. Furthermore, with a single common electrode contacting the second semiconductor regions, it is possible, among other things, to effectively reduce the parasitic capacitances of the semiconductor device as well as achieve dimensional scaling since ohmic contact to the conductive region can be made outside the fingers where physical dimensions are of no limitation.

Process for fabricating semiconductor devices with self-aligned contacts

A new self-aligned contact technology is afforded by semiconductor devices having a digitated electrode and a contiguous conductive region that contact first semiconductor regions and second semiconductor regions, respectively. The first semiconductor regions and the second semiconductor regions are formed in a semiconductor substrate, with each second semiconductor region underlying a finger of the digitated electrode. Advantageously, by forming a contiguous conductive region over the first semiconductor regions located between the fingers of the digitated electrode, it is not only possible to contact second semiconductor regions with a common electrode, but also to self-align the common electrode with the digitated electrode. Ohmic shorting between the digitated electrode and the contiguous conductive region is afforded by interposing an insulating region therebetween. Furthermore, with a single common electrode contacting the second semiconductor regions, it is possible, among other things, to effectively reduce the parasitic capacitances of the semiconductor device as well as achieve dimensional scaling since ohmic contact to the conductive region can be made outside the fingers where physical dimensions are of no limitation.

Self-aligned contact technology

A novel fabrication method is disclosed for fabricating a bipolar transistor having a digitated emitter electrode and a contiguous polysilicon region acting as a self-aligned base contact. The process substantially reduces the parasitic capacitances as well as eliminates the need for the intrinsic base region to be exposed to multiple etching, which results in the fabrication of small and reproducible base widths. A first polysilicon layer is deposited over the surface of a semiconductor substrate and, then, implanted with base dopants, which are driven into the surface of the active region by a furnace process for forming an intrinsic base region. Emitter dopants are next implanted into the first polysilicon layer. Subsequently, a nitride layer is deposited and the digitated emitter fingers patterned by selective etching. Link-up regions for connecting the intrinsic base region and the extrinsic base regions to be formed later is formed by implanting portions of the substrate free of the emitter fingers with base dopants. Next, oxide sidewalls are formed on the edges of the emitter fingers by depositing a conformal oxide layer and anisotropically etching the oxide layer, leaving vertical portions thereof on the edges of each emitter finger. Finally, a second polysilicon layer is deposited conformally over the entire structure and anisotropically etched back in order to form a planar, contiguous region between each finger of the digitated electrode. Implanting the entire structure with base dopants forms the extrinsic base regions outside the fingers of the digitated electrode. Heating the substrate to cause base dopants from the first polysilicon layer to diffuse into the substrate creates emitter regions under the fingers of the digitated electrode.

Process for fabricating a bipolar transistor with a self-aligned contact

A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks. All polycrystalline silicon layers in contact with the epitaxial layer are implanted with appropriate dopants such that these layers serve as reservoirs of dopant in order to simultaneously create the source and drain elements of the CMOS devices and the emitter elements of the bipolar devices during a heating step in the process. A tungsten layer is deposited over the polycrystalline layer in order to provide a conductive coupling to aluminum electrodes.

Process for manufacturing semiconductor BICMOS device

A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has a typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks. All polycrystalline silicon layers in contact with the epitaxial layer are implanted with appropriate dopants such that these layers serve as reservoirs of dopant in order to simultaneously create the source and drain elements of the CMOS devices and the emitter elements of the bipolar device during a heating step in the process. A tungsten layer is deposited over the polycrystalline layer in order to provide a conductive coupling to aluminum electrodes.

Growing community of inventors

Marlboro, NJ, United States of America

Tzu-Yin Chiu