Industrial Technology Research Institute

Macronix International Co., Ltd.

Tzu-Yi Yang

Huan-Ke Chiu

Yi-Chun Liu

Yeong-Lin Yu

Chia-Ming Tsai

Shen-Iuan Liu

Chih-Hong Lou

Kai-Cheung Juang

Tzuen-Hsi Huang

Gin-Kou Ma

Ting-Yu Liu

Ming-Ching Kuo

Che-Fu Liang

Chun-Ming Hsu

Ching-Feng Lee

Chung-Lin Tseng

Chao-Shiun Wang

Hsuan-Yu Tsai

Szu-Hsien Wu

Wei-Yang Ou

June-Ming Hsu

Zhi Wei Wang

Yung-Sheng Chen

Po-Hsuan Chang

Yung-Hsi Chang

A controlling method, a channel operating circuit and a memory system for executing a plurality of memory dies with single channel are provided. The plurality of memory dies correspond to a plurality of queue sections of a command queue. The controlling method comprises the following steps: A selecting unit selects one of the plurality of queue sections corresponding one of the plurality of memory dies which is riot at a busy state. An executing unit executes a command stored in one of the plurality of queue sections which is selected.

Controlling method, channel operating circuit and memory system for executing memory dies with single channel

A control method for a storage device is provided. The storage device includes a memory controller and a flash memory. The flash memory includes multiple blocks. The control method includes the following steps. Maintain a state table by the memory controller, wherein the state table records a disturbance count and a last check time of the blocks in the flash memory. Trigger a probe operation on a target block in the flash memory when at least one of the following conditions is met: (a) the disturbance count of the target block is greater than or equal to a disturbance count threshold; and (b) an elapsed time period of the target block is greater than or equal to an elapsed time threshold, wherein the elapsed time period of the target block starts from the last check time of the target block.

Storage device and associated control method to determine target memory blocks for probe operation

A request is received to load a particular overlay segment from a secondary storage memory to a main memory for execution by a processor, wherein the particular overlay segment is absent from the main memory. A determination is made whether the main memory can receive the particular overlay segment. In response to determining that the main memory cannot receive the particular overlay segment, eviction strategy information about one or more existing overlay segments that are present in the main memory is obtained. Based on the eviction strategy information, at least one of the one or more existing overlay segments is selected for eviction from the main memory. The particular overlay segment is retrieved from the secondary storage memory. The at least one of the one or more existing overlay segments in the main memory that is selected for eviction is replaced with the particular overlay segment.

Memory system and method for operating the same

A system for controlling excess bias of a single photon avalanche photo diode (SPAD) is provided. The system includes a power supply, a SPAD, a control circuit and a load. The power supply generates a supply voltage. The SPAD has a first terminal receiving the supply voltage and a second terminal generating an output voltage signal. The control circuit is connected to the second terminal of the SPAD. The load has a first terminal connected to the second terminal of the SPAD, and a second terminal connected to the control circuit for receiving a reset level. The control circuit is capable of monitoring a swing of the output voltage level and generating the reset level in response to the excess bias level and the swing of the output voltage level.

System and method for controlling excess bias of single photon avalanche photo diode

A system for providing, from a direct current (DC) voltage source, an alternating current (AC) to an electrical grid outputting a grid voltage, the system including: a transformer for coupling to the DC voltage source through a first switch controlled by a first control signal, and configured to provide a converted voltage based on a DC voltage; a rectifier coupled to the transformer, and configured to generate an envelope voltage of the converted voltage; a plurality of switches coupled to the rectifier to receive the generated envelope voltage of the converted voltage, the plurality of switches being controlled by a plurality of control signals, respectively, and configured to generate the AC from the generated envelope voltage of the converted voltage; and control apparatus coupled to the first switch and the plurality of switches, and configured to provide, based on the grid voltage, the first control signal and the plurality of control signals.

System for providing an alternating current, and control apparatus and method thereof

A frequency synthesizer and a method thereof. The method comprises grouping the carrier frequencies into first through fifth frequency groups comprising the first to third frequencies, the fourth to sixth frequencies, the seventh to ninth frequencies, the tenth to twelfth frequencies, and the thirteenth to fourteenth frequencies, generating a center frequency of the third frequency group, frequency mixing the center frequency of the third frequency group to produce center frequencies of the first, second, fourth, and fifth frequency groups, and performing frequency mixing on the center frequencies of the first through fifth frequency groups to produce two adjacent frequencies for each center frequency.

Frequency synthesizer and method thereof

A frequency synthesizer for generating a plurality of frequencies of a MB-OFDM UWB system is disclosed, wherein the frequencies include first to fourteenth frequencies from low to high and any of the adjacent two frequencies differs by a basic intervallic frequency. The frequency synthesizer includes a phase locked loop generating an initial signal with a frequency equal to the second frequency, an intervallic frequency generator generating first to third intervallic frequencies from low to high and all being integers times the basic intervallic frequency and generating a forth intervallic frequency equal to the basic intervallic frequency, and first to third mixers connected in series, respectively receiving the fourth intervallic frequency, one of the first to third intervallic, and the first intervallic frequency, to respectively generate the first to third frequencies, the fourth to ninth and the thirteenth to fourteenth frequencies, and the tenth to twelfth frequencies.

Frequency synthesizer and frequency synthesizing method

A programmable integer and fractional frequency divider is provided. The programmable divider divides a frequency of an input signal by a first divisor to generate an output signal, and comprises a programmable integer frequency divider and a fractional number switch. The programmable integer frequency divider divides the frequency of the input signal by a second divisor to generate the output signal, wherein the second divisor is first or second integers depending on a divisor switching signal. The fractional number switch calculates a pulse count of the output signal, and generates the divisor switching signal to switch from the first to the second integer when the pulse count of the output signal equals to a predetermined pulse count determined by a fractional part of the first divisor, and receives a fractional divisor control signal to change the predetermined pulse count, thereby changing the fractional part of the first divisor.

Programmable integer and fractional frequency divider

A resonant amplifier is provided. A resonant inductor is connected in series between a source (emitter) of a common gate (base) transistor and an input point (i.e. output point of previous stage), and a resonant capacitor is connected between the input point and a ground or a voltage source connected to a loading end, such that a lossy resonant cavity is formed for carrying out resonance to amplify the signal. Then, the amplified signal is drawn out by the common gate (base) architecture. Therefore, the gain of the resonant amplifier can be boosted at desired frequency.

Resonant amplifier

A receiving method for dual-mode receiver. When a received communication signal is a wideband signal, the dual-mode receiver is configured as a direct-conversion receiver, and when a received communication signal is a narrowband signal, the dual-mode receiver is configured as a low-IF receiver.

Dual-mode receiver and receiving method thereof

The present invention relates to a dual band transceiver architecture for wireless communication. A high frequency integrated circuit is used for converting down the received multi-mode frequency signal, and then a decoding circuit for base frequency will perform the processes of up-sampling and emitting a signal so as to transmit/receive the dual band signal by using a single frequency synthesizer.

Dual band transceiver architecture for wireless communication

The present invention relates to a signal modulation loop for the multi-mode mobile communication. The adaptive up-conversion modulation loop is applied in the multi-mode mobile communication, and is used for signal integration for the communication system comprising the second generation communication system, the global system for mobile communication (GSM), and the third generation communication system, the wideband code division multiple access (WCDMA), so as to achieve the object of multi-mode communication by using a single modulation loop.

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Hsinchu, Taiwan

Tzu-Yi Yang