Anpec Electronics Corporation

Tzu-Yang Yen

Chih-Yuan Chen

Hsin-Tai Lin

Ke-Horng Chen

Ping-yu Huang

A power converter having a high-side driving mechanism consuming low power is provided. A first terminal of a high-side switch is coupled to an input voltage. A second terminal of the high-side switch is connected to a first terminal of a low-side switch. A second terminal of the low-side switch is grounded. A first terminal of a bootstrap capacitor is connected to a node between the second terminal of the high-side switch and the first terminal of the low-side switch. A second terminal of the bootstrap capacitor is connected to a charging circuit. The charging circuit charges the bootstrap capacitor and detects data of the bootstrap capacitor. The charging circuit, according to the detected data of the bootstrap capacitor, determines whether or not to stop charging the bootstrap capacitor or to adjust charging of the bootstrap capacitor.

Power converter having high-side driving mechanism consuming low power

A power converter with a negative current detection mechanism is provided. A negative current detecting circuit includes a first operational amplifier, a first transistor and a second transistor. A non-inverting input terminal of the first operational amplifier is connected to a second terminal of a sense resistor. An inverting input terminal of the first operational amplifier is connected to a first terminal of a first capacitor. Control terminals of the first and second transistors are connected to an output terminal of the first operational amplifier. A first terminal of the first transistor is connected to the second terminal of the sense resistor. A second terminal of the first transistor is grounded. A first terminal of the second transistor is connected to the inverting input terminal of the first operational amplifier and the first terminal of the first transistor. A second terminal of the second transistor is grounded.

Power converter having negative current detection mechanism

A power failure prevention system includes a switch circuit, an energy storage circuit, a voltage detector circuit and a control circuit. The switch circuit includes a first switch, a second switch, a third switch and a fourth switch. The energy storage circuit is connected to the switch circuit. The voltage detector circuit detects an input voltage provided by an input voltage source and a stored voltage of the energy storage circuit. The control circuit controls the switch circuit according to the detected input voltage and stored voltage. When the input voltage is higher than a first threshold, the switch circuit allows the input voltage to charge the energy storage circuit. When the input voltage is lower than a second threshold, the switch circuit allows the stored voltage to discharge to the input voltage source. The first threshold is higher than the second threshold.

Power failure prevention system

A multi-phase DC-DC power converter includes an error amplifier, a comparator, a phase selection circuit, a plurality of phase circuits and a width detecting circuit. The plurality of phase circuits are each associated with a phase of the multi-phase DC-DC power converter, each including a turn-on clock generation circuit, a first switching transistor, a second switching transistor, an output inductor, and a control logic. In a load transition state, when the width detecting circuit detects that a comparison output signal exceeds a predetermined width, the phase selection circuit adjusts one of the plurality of phase signals based on a force trigger signal, and outputs, corresponding to a force trigger signal, one of the plurality of on-signals.

Multi-phase DC-DC power converter and driving method of the same

A system and a method for improving continuous load transition of a DC-DC converter are provided. The system includes a conduction detector circuit, a counter circuit, a depth control circuit and a slope generator. The conduction detector circuit detects a phase signal of the DC-DC converter to generate a pulse signal. The counter circuit counts the number of pulse waves of the pulse signal to output a counting signal. The depth control circuit generates a pulled-down depth signal. The slope generator generates a slope signal according to the pulled-down depth signal. The pulled-down depth signal is pulled down by a first depth each time the switch circuit is conducted, but when the number of times that the switching circuit is conducted reaches a conduction number threshold, the pulled-down depth signal is pulled down by a second depth that is larger than the first depth.

System and method for improving continuous load transition of DC-DC converter

A multi-phase DC-DC power converter includes an error amplifier, a comparator, a phase selection circuit, a plurality of phase circuits and a PFM/PWM logic control circuit. The plurality of phase circuits are each associated with a phase of the multi-phase DC-DC power converter, each including a turn-on clock generation circuit, a first switching transistor, a second switching transistor, an output inductor, a zero-crossing detection circuit, and a control logic. The PFM/PWM logic control circuit is configured to output, in response to a PFM control signal and a control signal associated with switch signals, a first PFM control signal and a second PFM control signal to a first phase circuit and a second phase circuit of the plurality of phase circuits. The PFM/PWM logic control circuit enters a first phase, a second phase, and a third phase under a light load condition or a no load condition.

A frequency compensation circuit includes a compensation circuit and a calculation circuit. The compensation circuit controls the calculation circuit to generate a ramp voltage when the voltage at a node between an upper-side switch and a lower-side switch of the DC voltage converter is larger than an input voltage of the DC voltage converter. The calculation circuit generates a control signal at low level when the ramp voltage is smaller than the output voltage of the DC voltage converter so that the frequency compensation circuit generates the constant on-time signal at high level. The calculation generates the control signal at high level when the ramp voltage is larger than or equal to the output voltage of the DC voltage converter so that the frequency compensation circuit generates the constant on-time signal at low level.

Frequency compensation circuit used in DC voltage converter

A current balance circuit is used in a multiphase converter, and the multiphase converter includes power stage circuits, the current balance circuit and a control circuit. The current balance circuit includes detection units, a calculation circuit and error amplifiers. Detection units obtain the output power information of their corresponding power stage circuits. After each error amplifier compares the obtained output power information with the average of all output power information, it amplifies differences between the output power information and the average of all output power information and converts the amplified differences to current information, such that the control circuit adjusts currents provided by the power stage circuits according to the current information from the error amplifiers to balance the currents provided by the power stage circuits.

Current balance circuit and multiphase converter using the same

Provided herein are a single-inductor dual-output (SIDO) power converter operable in a discontinuous conduction mode and a control method thereof. The SIDO power converter is operable to switch between a boost mode and a buck-boost mode. The SIDO power converter dynamically adjusts output timings of clock signals with respect to the loads according to a load difference therebetween to lower the power consumption with a light load when the inductor current is zero to achieve optimal power distribution.

SIDO power converter operable in discontinuous conduction mode and control method thereof

The present disclosure illustrates a single-inductor dual-output (SIDO) power converter for hysteresis current control mode and a control method thereof. In the SIDO power converter provided by the instant disclosure, a detecting circuit, connected to the upper bridge transistor, determines whether the inductive current reaches the upper limit threshold or the lower limit threshold, and further drives a control circuit to turn on or off the corresponding upper bridge transistor and/or the lower bridge transistor, so as to simplify the operation of the hysteresis current control mode.

Single-inductor dual-output (SIDO) power converter for hysteresis current control mode and control method thereof

A zero current detecting circuit is disclosed. The zero current detecting circuit includes a first zero current comparator for determining current variation on an inductor of a synchronous switching power converter so as to output a zero current signal to turn off a down-bridge transistor of the synchronous power converter; a second zero current comparator for determining whether the first zero current comparator turns off the down-bridge transistor too early or too late and outputting a comparison result; a counter coupled to the second zero current comparator for ascending or descending a control bit according to the comparison result, and an adjustable delay unit coupled to the first zero current comparator and the counter for adjusting a delay time according to the control bit, and delaying and outputting the zero current signal according to the delay time, to compensate a negative offset voltage by delay.

Zero current detecting circuit and method and related synchronous switching power converter

An audible noise avoiding circuit and a DC-DC boost converter for a DC-DC boost converter are provided. The audible noise avoiding circuit comprises a timing controller and a linear regulator. The timing controller discharges a timing capacitor to a low voltage according to switching of the DC-DC boost converter. A sink output stage of the liner regulator is coupled to the output voltage node. When the voltage of the timing capacitor is higher than a threshold voltage, the compensation unit compensates the output of the operational amplifier for gradually turning on the sink output stage in order to gradually reduce the voltage of the output voltage node. A predetermined charging time interval is defined by the time interval of charging the timing capacitor from the low voltage to the threshold voltage, the reciprocal of the predetermined time interval is a frequency in the ultrasonic wave frequency range.

Audible noise avoiding circuit and DC-DC boost converter having the same

The synchronous switching power converter comprises an inductor; a down bridge transistor; and a zero current detection circuit comprising a zero current comparator for receiving a fixed comparing level at a negative input end for comparison to change state of a comparing result; a delay unit, for delaying the comparing result to change state of a turn off signal according to a compensation voltage, to turn off the down bridge transistor when determining current on the inductor is zero; a transient state adjusting circuit for indicating a transient period when detecting state of the turn off signal is changed; and an integrator for integrating the compensation voltage by analog manner to adjust value of the compensation voltage and providing to the delay unit within the transient period; wherein the zero current comparator determines the integrator to integrate positively or negatively within the transient period.

Synchronous switching power converter with zero current detection, and method thereof

A constant-on-time generation circuit for generating a turn-on signal to a buck is disclosed. The constant-on-time generation circuit includes a capacitor, a current source, a second resistor, an inverter, a transistor coupled to the inverter for generating a set turn-on signal according to a first front-end driver signal of the buck converter, a comparator including a negative input terminal coupled to a reference voltage, a positive input terminal coupled to the second resistor and the current source, and an output terminal, for comparing the reference voltage with the set turn-on signal to output a comparison result, and an SR-latch for outputting a turn-on signal to a driver stage circuit of the buck converter according to a trigger signal of the buck converter and the comparison result.

Constant-on-time generation circuit and buck converter

A zero current detecting circuit is disclosed. The zero current detecting circuit includes a first zero current comparator for determining current variation on an inductor of a synchronous switching power converter so as to accordingly turn off a down-bridge transistor of the synchronous power converter; a second zero current comparator for determining whether the first zero current comparator turns off the down-bridge transistor too early or too late and outputting a comparison result, and a counter coupled to the second zero current comparator for ascending or descending a control bit according to the comparison result.

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Taipei, Taiwan

Tzu-Yang Yen