Taiwan Semiconductor Manufacturing Comp. Ltd.

Tzu-Yang Wu

Sheng-Liang Pan

Ya-Wen Lee

Chin-Hsiang Lin

Tsai-Sheng Gau

Ruei-Hung Jang

Chia-Hung Kao

Sheng-Chieh Liu

Hsueh-Liang Chou

Kun-Ming Huang

Fu-Hsin Chen

Shih-Shiung Chen

Fei-Yuh Chen

Fei-Yun Chen

Yuh-Hwa Chang

Eugene Chu

Wei-Ya Wang

Yuan-Bang Lee

Jeffery Chu

Yj Wang

Ying-De Chen

Disclosed is a method and a system for forming alignment marks on a transparent substrate. A light reflective layer is deposited over an optically transparent substrate of a wafer. A region is defined around an alignment mark on the optically transparent substrate. The light reflective layer is removed from a substantial portion of the transparent substrate excluding the region. In addition, a micro electro-mechanical systems device is disclosed. The device comprises an optically transparent substrate, at least one optically partially transparent alignment mark on the optically transparent substrate, and a plurality of reflective elements or imaging pixels attached to the optically transparent substrate.

Method and system for patterning alignment marks on a transparent substrate

Disclosed is a method and a system for wafer backside alignment. A zero mark patterning on front side of a substrate. A plurality of layers are deposited on the front side of the substrate. The wafer is flipped over with backside of the substrate facing up, and a through wafer etching is performed from the backside to an etch stop layer deposited over the front side of the substrate.

Method and system for wafer backside alignment

A method for wafer backside alignment overlay accuracy includes forming a buried layer on a front-side of a wafer; forming a conductive layer on the buried layer and patterning a first test structure and a second test structure therein; forming an etch stop layer on the conductive layer; etching through the wafer from the backside to perform an alignment process with the first test structure; and determining an overlay accuracy of the alignment process with the second test structure. The first test structure includes an optical vernier and the second test structure includes an electrical testing structure.

Method and device for wafer backside alignment overlay accuracy

A method for releasing a micromechanical structure. A substrate is provided. At least one micromechanical structural layer is provided above the substrate, wherein the micromechanical structural layer is sustained by a sacrificial layer of a silicon material. An amine-based etchant is provided to etch the silicon material. That is, during performing a post-cleaning procedure with an amine-based etchant, polymer residue and the sacrificial layer of silicon can be simultaneously removed without any additional etching processes.

Method for releasing a micromechanical structure

An MEMS mirror structure is formed using an etching process that forms sidewall oxide spacers while maintaining the integrity of the oxide layer formed over the reflective layer of the MEMS mirror structure. The discrete mirror structure is formed to include a reflective layer sandwiched between oxide layers and with a protect layer formed over the upper oxide layer. A spacer oxide layer is formed to cover the structure and oxide spacers are formed on sidewalls of the discrete structure using a selective etch process that is terminated when horizontal portions of the spacer oxide layer have cleared to expose the release layer formed below the discrete mirror structure and the protect layer. The superjacent protect layer prevents the spacer oxide etch process from attacking the upper oxide layer and therefore maintains the integrity of the upper oxide layer and the functionality of the mirror structure.

Surface MEMS mirrors with oxide spacers

A capacitor structure which has generally pyramidal or stepped profile to prevent or reduce dielectric layer breakdown is disclosed. The capacitor structure includes a first conductive layer, at least one dielectric layer having a first area provided on the first conductive layer and a second conductive layer provided on the at least one dielectric layer. The second conductive layer has a second area which is less than the first area of the at least one dielectric layer. A method of fabricating a capacitor structure is also disclosed.

Pyramid-shaped capacitor structure

Growing community of inventors

Hsinchu, Taiwan

Tzu-Yang Wu