Ali Corporation

Tzu-Wei Lan

Chih-Yu Chuang

Wei-Jian Lin

Wei-Hsien Fang

Provided is a layout structure adapted for a signal format converter. The layout structure includes a first and a second capacitor array. The first capacitor array is disposed on one side of a reference axis, and includes multiple first capacitor units that form multiple first capacitors. The first capacitors respectively have multiple first capacitances. The second capacitor array is disposed on the other side of the reference axis, and includes multiple second capacitor units that form multiple second capacitors. The second capacitors respectively have multiple second capacitances. The first capacitors respectively correspond to the second capacitors. Each first capacitor and each corresponding second capacitor are symmetrical with respect to the reference axis, or each first capacitor and each corresponding second capacitor are separated from each other by the same distance. Each first capacitor and each corresponding second capacitor have the same capacitance.

Layout structure with minimal additional parasitic capacitance

A capacitor array structure which includes N capacitor units is provided. Each capacitor unit includes a first metal layer, a second metal layer, and a third metal layer to form an upper electrode and a lower electrode. The second metal layer is disposed between the first metal layer and the third metal layer, and includes a second patterned metal portion of the lower electrode and a first patterned metal portion of the upper electrode. disposed above. The second patterned metal portion of the lower electrode has an opening, and a side of the first patterned metal portion of the upper electrode is exposed in the opening, such that the side of the first patterned metal portion of the upper electrode is adjacent to the lower electrode of another capacitor unit.

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Hsinchu, Taiwan

Tzu-Wei Lan