Siliconsystems, Inc.

Texas Instruments Corporation

Tzu-Wang Pan

Richard G Yamasaki

Jenn-Gang Chern

An improved Viterbi detector for use in a partial-response maximum-likelihood (PRML) channel. The present invention reduces the amount of hardware necessary in the conventional digital implementation, as well as increasing the speed of the system, by utilizing analog circuits. Whereas prior art analog implementations use more complex hardware and less efficient algorithms, the present invention utilizes easily realizable circuitry to perform a more efficient algorithm. A sampled data Viterbi detector compares a sampled analog input signal with two threshold signals. The binary outputs of the comparing means are then provided to a survival sequence register, as well as being used to formulate new threshold signals for the subsequent input sample. The hardware implements Ferguson's method for calculating sequence metrics by representing the accumulated metric difference as two threshold signals. Probability based decisions are then performed in analog comparators. Because Ferguson's method only requires formulation of the difference between metrics rather than formulation of the true metrics themselves, the successive threshold signals that represent this difference can be generated using multi-input track and hold circuits and a voltage summing means.

Method and apparatus for implementing a viterbi detector for PRML

An improved adaptive three tap transversal equalizer for partial-response signaling. The invention reduces the complexity of the hardware, as well as reducing the sensitivity of the equalizer to gain and timing errors. The present invention employs an algorithm based on sample values around zero. The resulting decrease in average magnitude of the error results in decreased sensitivity to gain errors. The algorithm of the present invention improves cancellation of sample timing errors. In the present invention, the coefficient of an adaptive cosine equalizer is updated by integration of a stochastic gradient. To calculate the gradient, the product of the quantized output from the previous sample and the output from the present sample is summed together with the product of the output from the previous sample and the quantized output from the present sample. In addition, the equalizer output is masked such that values quantizing to non-zero values are discarded in the update algorithm. In systems employing separate adaptive loops for gain control, timing recovery and equalization, the amount of undesired loop interaction is much reduced from that of prior art methods.

Method and apparatus for an adaptive three tap transversal equalizer for

A timing acquisition circuit using a phase locked loop with programmable damping for either Type A or Type B phase detectors is described. In the damping scheme for a Type A phase detector, a resistance (R1) is simulated by adding an equivalent voltage Veff to the capacitor voltage. The equivalent voltage Veff is generated internally, so that programmable damping is made possible. In Type B phase detectors, a variable gain amplifier is used to control the effective resistance (R1) of the loop filter.

Method and apparatus for programmable damping factor of a phase locked

A method and apparatus for timing acquisition of partial response class IV Signaling is described. The invention uses an acquisition logic block to determine an output sequence that best matches a preamble pattern. The logic block analyzes current quantizer output X and the two previous decisions X.sub.n and X.sub.n-1. The logic uses these values to determine the next value X.sub.n+1 so that the best match occurs. The invention is implemented with OR gates, AND gates, and D flip-flops and can operate in acquiring mode or tracking mode.

Method and apparatus for timing acquisition of partial response class IV

The present invention describes an improved RLL channel utilizing a closed-loop clock recovery scheme and a simplified decoding algorithm. (1,7) run-length-limited (RLL) code is used to reduce the magnetic nonlinearity problem posed by prior art PRML systems. In the preferred embodiment of the present invention, the analog data signal amplified, filtered and equalized to approximate an ideal waveform. The signal is then sampled and decoded into binary data. The clock recovery circuit is designed to sample the analog data such that the signal peak lies centered between consecutive sample points. It is thus made possible for the phase error to be extracted from a direct comparison of neighboring sample values. The phase error is then used to adjust the clock signal for the following samples. In the decoding algorithm of the present invention, by making useful approximations, the complexity of the decision functions is reduced, along with the number of required look-ahead samples. The reduction in look-ahead samples reduces the system's sensitivity to misequalization.

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Irvine, CA, United States of America

Tzu-Wang Pan