Vanguard International Semiconductor Corporation

Advanced Ion Beam Technology, Inc.

Tzu-Shih Yen

Erik S Jeng

Daniel Tang

Fu-Liang Yang

Hao-Chieh Liu

Hung-Yi Luo

Eddy Chiang

Hsiu-Lan Lee

Wen-Shiang Liao

Chun-Yao Chen

Bi-Ling Chen

Rong-Wu Chien

Hsiao-Chin Tuan

Wan-Yih Lien

Bih-Tiao Lin

Tsungnan Cheng

I-Ping Lee

Pei-Wen Li

Chi-San Wu

Jong-Bor Wang

A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.

Replacement source/drain finFET fabrication

In doping a non-planar semiconductor device, a substrate having a non-planar semiconductor body formed thereon is obtained. A first ion implant is performed in a region of the non-planar semiconductor body. The first ion implant has a first implant energy and a first implant angle. A second ion implant is performed in the same region of the non-planar semiconductor body. The second ion implant has a second implant energy and a second implant angle. The first implant energy may be different from the second implant energy. Additionally, the first implant angle may be different from the second implant angle.

Doping a non-planar semiconductor device

In plasma doping a non-planar semiconductor device, a substrate having a non-planar semiconductor body formed thereon is obtained. The substrate having the non-planar semiconductor body may be placed into a chamber. A plasma may be formed in the chamber and the plasma may contain dopant ions. A first bias voltage may be generated to implant dopant ions into a region of the non-planar semiconductor body. A second bias voltage may be generated to implant dopant ions into the same region. In one example, the first bias voltage and the second bias voltage may be different.

Plasma doping a non-planar semiconductor device

A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched to expose a first region of the fin. A portion of the first region is then doped with a dopant.

The present invention discloses a method for simultaneously removing from a silicon surface polymeric films and damaged silicon layers by exposing the surface to a cleaning solution that contains amine or ethanolamine for a length of time that is sufficient to remove all such unwanted materials. The method is effective in cleaning away damaged silicon layers having a thickness between about 20 &angst; and about 60 &angst; in a period of time between about 2 minutes and about 20 minutes. In a preferred embodiment, the cleaning solution is a water solution of ethanolamine and gallic acid.

Method for removing etch-induced polymer film and damaged silicon layer from a silicon surface

A method for forming a via through a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a patterned silicon nitride layer which defines a contact region beneath the patterned silicon nitride layer. There is then formed over the patterned silicon nitride layer a silicon oxide layer. There is then etched the silicon oxide layer while employing a reactive ion etch (RIE) method employing a first etchant gas composition comprising a fluorocarbon etchant gas to form: (1) an etched silicon oxide layer which exposes the contact region without substantially etching the patterned silicon nitride layer; and (2) a fluorocarbon polymer residue layer formed upon at least one of the etched silicon oxide layer and the patterned silicon nitride layer. Finally, there is stripped from the substrate the fluorocarbon polymer residue layer while employing a downstream plasma etch method employing a second etchant gas composition comprising a fluorocarbon etchant gas and oxygen. The method may also be employed in general for etching silicon oxide layers in the presence of silicon nitride layers. Similarly, the method may also in general be employed in removing fluorocarbon polymer residue layers from integrated circuit layers including but not limited to silicon oxide layers and silicon nitride layers.

Multiple etch contact etching method incorporating post contact etch etching

A method for forming self-aligned contact (SAC) is disclosed to improve device reliability. The method includes forming a dielectric liner over the contact opening before the contact plug is filled in. Optional contact implantation before and after the liner formation can be added to enhance the doping profile of the device.

Method for forming self-aligned contact with liner

A method for making self-aligned contacts on a semiconductor substrate using a hard mask. After the transistor is formed, a blanket insulating layer is formed on said semiconductor substrate. A hard mask having openings on the blanket insulating layer is formed over the insulating layer. The openings overlay the source/drain region and part of the gate electrode structure. Using the patterned hard mask, the insulating layer is etched to the gate electrode protecting layer. Then self-aligned contacts is completed by etching the insulating layer to expose the source/drain regions using the gate electrode protecting layer and the insulating sidewall spacers as the mask.

Method for forming self-aligned contacts using a hard mask

A method for fabricating semiconductor device is disclosed herein. The first step is to form a first oxide layer on a substrate. Subsequently formed are polycrystalline silicon layer, a polycide layer, optionally a second oxide layer, and a silicon nitride layer on the first oxide layer. A photoresist pattern on the silicon layer is formed thereafter, and the silicon nitride layer is etched using the photoresist pattern as a mask to expose a portion of the polycide layer. The photoresist pattern is then, the polycide layer is isotropically etched to form an under cut in the polycide layer under the etched nitride layer (optional second oxide layer). The width of the top portion of the isotropically etched polycide layer is smaller than the width of the etched nitride layer. The isotropically etched polycide layer is then anistropically etched, and the polycrystalline layer is etched to expose a portion of the first oxide layer to form a multi-layer structure. Finally, spacers on side-walls of the multi-layer structure are formed to create the semiconductor device, the side-wall of the anisotropicaly etched polycide layer generated after the oxidation process is prevented from penetrating the spacer of the semiconductor device according to the present invention.

Method for forming a semiconductor device

A method of removing microscratches in planarized dielectric surfaces covering conductor layers in submicron integrated circuit structures includes a semiconductor substrate having at least one dielectric layer formed thereon followed by a chemical mechanical polishing process for planarization. The removal of microscratches includes depositing a PE-CVD polymer layer to fill the microscratches, caused by CMP planarization, and to cover the planarized dielectric surface with a thin layer of the polymer. Deposition is followed by introducing an etching gas into the CVD chamber for an etch back of the just deposited polymer to well below the depth of the microscratches wherein the deposited polymer has the same etch rate as the dielectric layer formed thereunder.

Method for eliminating CMP induced microscratches

A method of fabrication of a storage capacitors for DRAM memory cells using silylated photoresist is described. Partially completed DRAM memory cells comprising wordline transistor gates and bitline source and drain regions is provided. Conductive plugs are provided through a dielectric layer to the top surfaces of the bitline drain regions. A first conductive layer is deposited overlying the conductive plugs. A photoresist layer is deposited overlying the first conductive layer. The photoresist layer is etched to define the areas for the lower plates of the storage capacitors. The photoresist is exposed to a silylating agent to form a silylated layer. The top layer of the silylated photoresist is etched through to form a mask for subsequent etching. The photoresist layer is etched as defined by the mask. The first conductive layer is etched as defined by the mask to form the shape of the lower nodes of the storage capacitors. The remaining silylated photoresist is removed. A capacitor dielectric layer is deposited overlying the lower nodes of the storage capacitors. A second conductive layer is deposited to form the upper nodes of the storage capacitors. A passivation layer is deposited to complete fabrication.

Method to fabricate capacitor structures with very narrow features using

A process for fabricating an interconnect structure, featuring contact of the interconnect structure, to an exposed side of an underlying conductive plug structure, where the conductive plug structure is used to communicate with an active device region in a semiconductor substrate, has been developed. The process features the use of simple photolithographic patterns, such as a stripe opening, exposing a group of gate structures, and a group of spaces, located between the gate structures, to be used for subsequent contact plug formation. This is in contrast to conventional processing, in which a more difficult photolithographic procedure is used to create smaller, individual openings, to individual spaces between gate structures. In addition this invention features a self-aligned opening, exposing only a side of a contact plug structure. An overlying interconnect structure then contacts only the exposed side of the underlying contact plug structure, again reducing photolithographic difficulties, encountered with conventional methods of creating a non-self aligned opening to an underlying contact plug.

Method for fabricating ultra-small interconnections using simplified

A process for simultaneously forming storage node structures, for a DRAM cell, and an interconnect structure, for a peripheral region of a DRAM chip, has been developed. The process features the use of dual damascene procedures, with the first damascene procedure used to create the storage node, and interconnect structures, followed by a second damascene procedure, used to create plug structures, used to contact the underlying storage node and interconnect structures. This invention also features the use of SAC openings, allowing the formation of the SAC storage node structures to be realized.

Method for simultaneously fabricating capacitor structures, for giga-bit

A method for removing from a patterned silicon containing dielectric layer a patterned partially fluorinated photoresist layer employed in patterning the patterned silicon containing dielectric layer. There is first formed over a semiconductor substrate a metal contact layer having a silicon containing dielectric layer formed thereover. There is then formed upon the silicon containing dielectric layer a patterned photoresist layer. There is then formed by use of a reactive ion etch (RIE) plasma etch method employing a fluorine containing etchant a via through the silicon containing dielectric layer to form a patterned silicon containing dielectric layer reaching the metal contact layer. The reactive ion etch (RIE) plasma etch method simultaneously forms from the patterned photoresist layer a partially fluorinated patterned photoresist layer comprising a patterned fluorinated surface layer of the partially fluorinated patterned photoresist layer and a patterned non-fluorinated underlying remainder layer of the partially fluorinated patterned photoresist layer. The reactive ion etch (RIE) plasma etch method also simultaneously forms upon the sidewalls of the via a metal-polymer residue layer. There is then removed, at least partially, the patterned fluorinated surface layer of the partially fluorinated patterned photoresist layer through a first stripping method employing an argon containing plasma under conditions such that the metal-polymer residue layer is not substantially oxidized. Finally, there is then removed through a second stripping method at least the metal-polymer residue layer from the sidewalls of the via.

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Hsinchu, Taiwan

Tzu-Shih Yen