United Microelectronics Corp.

Tzu-Ping Chen

Chien-Hung Chen

Chih-Haw Lee

Chih-Jung Chen

Yu-Jen Chang

Wen-Chung Chang

Ming-Tzong Yang

Shen-De Wang

Nai-Chen Peng

Kuang-Pi Lee

Chun-Lung Chang

Pei-Chen Kuo

Kuan-Yi Tseng

Wei-Shiang Huang

A semiconductor memory device includes a select transistor and a floating gate transistor on a substrate. The select transistor includes a select gate, a select gate oxide layer and a drain doping region. The floating gate transistor includes a floating gate, a floating gate oxide layer, a source doping region, a first tunnel doping region and a second tunnel doping region under the floating gate, a first tunnel oxide layer on the first tunnel doping region, and a second tunnel oxide layer on the second tunnel doping region. The floating gate oxide layer is disposed between the first tunnel oxide layer and the second tunnel oxide layer. A lightly doped diffusion region surrounds the source doping region and the second tunnel doping region.

Semiconductor memory device

A split-gate flash memory cell includes a semiconductor substrate having thereon a select gate oxide layer and a floating gate oxide layer. A floating gate is disposed on the floating gate oxide layer. A football-shaped oxide layer is disposed on the floating gate. The floating gate includes tips under the football-shaped oxide layer. A select gate is disposed on the select gate oxide layer and extended onto the football-shaped oxide layer. An inter-poly oxide layer is between the select gate and the floating gate. The inter-poly oxide layer has a thickness smaller than a thickness of the select gate oxide layer. A source region is formed in the semiconductor substrate and adjacent to the floating gate. A drain region is formed in the semiconductor substrate and adjacent to the select gate.

Split-gate flash memory cell and fabrication method thereof

A method for fabricating a semiconductor device includes the steps of providing a semiconductor substrate; forming a tunnel dielectric on the semiconductor substrate; forming a floating gate on the tunnel dielectric; forming an insulation layer conformally disposed on the top surface and the sidewall surface of the floating gate; forming a control gate disposed on the insulation layer and the floating gate; and forming a spacer continuously distributed on the sidewall surfaces of the floating gate and the control gate, where the spacer overlaps portions of the top surface of the floating gate.

Method of fabricating semiconductor device

A semiconductor device includes a semiconductor substrate, an isolation structure; a first gate dielectric layer and a first gate electrode. The isolation structure is formed in the semiconductor substrate to divide the semiconductor substrate at least into a first active region and a second active region. The first gate dielectric layer is disposed on the first active region, and has a plane top surface contacting to a sidewall of the isolation structure and forming an acute angle therewith. The first gate electrode stacked on the plane top surface.

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device includes providing a substrate having a first device region and a second device region. Floating gate structure is formed in the first device region. Liner layer and nitride layer are sequentially deposited over the first device region and the second device region. The floating gate structure is conformally covered. Etching back process is performed on the nitride layer to reduce thickness of the nitride layer. The first device region is still covered by the nitride layer. A photomask layer is formed over the substrate with an opening region to expose the second device region for cleaning. The photomask layer is removed. A gate oxide layer grows on the substrate in the second device region. Anisotropic etching process is performed to remove the nitride layer, resulting in a nitride spacer on a lower portion of a sidewall of the floating gate structure.

Method for fabricating semiconductor device

A semiconductor device includes a semiconductor substrate, a tunnel dielectric disposed on the semiconductor substrate, a floating gate disposed on the tunnel dielectric, a control gate disposed on the floating gate, and an insulation layer disposed between the floating gate and the control gate. The semiconductor device further includes a spacer continuously distributed on the sidewall surfaces of the floating gate and the control gate, and the spacer overlaps portions of the top surface of the floating gate.

Semiconductor device and a method of fabricating the same

A single poly electrical erasable programmable read only memory (EEPROM) includes a source, a drain, a dielectric layer and an electrode layer. The source and the drain are located in a substrate, wherein the source and the drain have a first conductive type. The dielectric layer is disposed on the substrate and between the source and the drain, wherein the dielectric layer includes a first dielectric layer having two tunnel dielectric parts separating from each other, and thicknesses of the two tunnel dielectric parts are thinner than thicknesses of the other parts of the first dielectric layer. The electrode layer is disposed on the dielectric layer, wherein the electrode layer includes a first electrode disposed on the first dielectric layer, thereby the first electrode being a floating gate.

Single poly electrical erasable programmable read only memory (EEPROM)

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a dielectric stack is formed on the substrate, in which the dielectric stack includes a first silicon oxide layer and a first silicon nitride layer. Next, the dielectric stack is patterned, part of the first silicon nitride layer is removed to form two recesses under two ends of the first silicon nitride layer, second silicon oxide layers are formed in the two recesses, a spacer is formed on the second silicon oxide layers, and third silicon oxide layers are formed adjacent to the second silicon oxide layers.

Method for fabricating a flash memory

The present invention provides a non-volatile memory structure, which includes a substrate, a gate dielectric layer disposed on the substrate, two charge trapping layers, disposed on two sides of the gate dielectric layer respectively and disposed on the substrate, a gate conductive layer disposed on the gate dielectric layer and on the charge trapping layers, wherein a sidewall of the gate conductive layer is aligned with a sidewall of one of the two charge trapping layers, and at least one vertical oxide layer, disposed beside the sidewall of the gate conductive layer.

Non-volatile memory structure and manufacturing method thereof

A method of forming a semiconductor device is disclosed. A sacrificial oxide layer is formed on a substrate having first and second areas. Using a photoresist mask exposing the first area and covering the second area as a mask layer, by a wet etching process, the sacrificial oxide layer in the first area and an edge portion of the sacrificial oxide layer in the second area are simultaneously removed, wherein the sacrificial oxide layer remained in the second area has a sidewall with a slope smaller than 40 degrees. An oxide-nitride-oxide (ONO) layer is formed over the first and second areas. The sacrificial oxide layer and the ONO layer formed thereon in the second area are removed, so that the ONO layer remained in the first area forms a first gate insulating layer in the first area. A second gate insulating layer is formed in the second area.

Method of forming semiconductor device

A semiconductor device is disclosed. The semiconductor device includes: a substrate; a floating gate on the substrate; a first silicon oxide layer between the floating gate and the substrate; a first tunnel oxide layer and a second tunnel oxide layer adjacent to two sides of the first silicon oxide layer; and a control gate on the floating gate. Preferably, the thickness of the first tunnel oxide layer and the second tunnel oxide layer is less than the thickness of the first silicon oxide layer.

A gate structure is provided. The gate structure includes a substrate, a gate disposed on the substrate and a gate dielectric layer disposed between the substrate and the gate, wherein the gate dielectric layer is in the shape of a barbell. The barbell has a thin center connecting to two bulging ends. Part of the bulging ends extends into the gate and the substrate.

Semiconductor structure and a fabricating method thereof

A method for fabricating semiconductor device is disclosed. The method includes the steps of first providing a substrate, in which the substrate includes a SONOS region and a EEPROM region. Next, a first gate layer is formed in the SONOS region and the EEPROM region, the first gate layer is patterned by removing the first gate layer from the SONOS region and forming a floating gate pattern in the EEPROM region, an ONO layer is formed in the SONOS region and the EEPROM region, a second gate layer is formed on the ONO layer of the SONOS region and the EEPROM region, the second gate layer and the first gate layer are patterned to form a floating gate and a control gate in the EEPROM region, and the second gate layer is patterned to form a first gate in the SONOS region.

A nonvolatile memory device comprises a substrate, a gate electrode, a single charge trapping sidewall and a source/drain region. The gate electrode is disposed on and electrically isolated from the substrate. The single charge trapping sidewall is disposed adjacent to a sidewall of the gate electrode and electrically isolated from the substrate and the gate electrode, so as to form a non-straight angle between the substrate and the single charge trapping sidewall. The source/drain region is disposed in the substrate and adjacent to the gate electrode.

Growing community of inventors

Hsinchu County, Taiwan

Tzu-Ping Chen