Taiwan Semiconductor Manufacturing Comp. Ltd.

Tzu-Jin Yeh

Hsieh-Hung Hsieh

Chewn-Pu Jou

Jun-De Jin

Ho-Hsiang Chen

Ying-Ta Lu

Hsien-Yuan Liao

Chi-Hsien Lin

Chia-Chung Chen

En-Hsiang Yeh

Wen-Sheng Chen

Chi-Feng Huang

Hong-Lin Chu

Ming Hsien Tsai

An-Hsun Lo

Fu-Lung Hsueh

Yen-Jen Chen

Victor Chiang Liang

Fu-Huan Tsai

Han-Min Tsai

Chiao-Han Lee

Sally Liu

Shu Fang Fu

Ru-Gun Liu

Hua-Chou Tseng

Ming-Hsien Tsai

Sa-Lly Liu

Yi-Hsuan Liu

Chien-Chih Ho

Wu-Chen Lin

Garming Liang

Simon Chai

Hsiao-Tsung Yen

Huan-Neng Chen

Fan-Ming Kuo

Min-Chie Jeng

Tzong-Lin Wu

Hsien-Chang Wu

Mei-Show Chen

Jhe-Ching Lu

Hsiao-Chun Lee

Shu-Ying Cho

Yu-Tai Chia

Chia-Ming Liang

Po-Yi Wu

Zong-You Li

Ming-Ta Yang

Kal-Wen Tan

Chung-Ho Chai

Hsiu-Wen Wu

A semiconductor device is provided. The semiconductor device includes a substrate, a transistor, at least one isolation and at least one non-doped region. The substrate includes a lower portion. The transistor is disposed on the lower portion. The at least one isolation is adjacent to the transistor, and disposed on the lower portion. The at least one non-doped region is disposed between and adjacent to the isolation and the lower portion.

Semiconductor device for a low-loss antenna switch

A semiconductor device includes a substrate, a first metal-oxide-semiconductor device and a at least one first resistor. The substrate includes a non-doped region. The first metal-oxide-semiconductor device extends into the substrate. The first metal-oxide-semiconductor device is adjacent to the non-doped region. The at least one first resistor is disposed right above the non-doped region and arranged in a first row aligned with the first metal-oxide-semiconductor device in a first direction.

The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device comprises a substrate, a first gate electrode, a second gate electrode, a first doped region, a second doped region, a third doped region, and a first interconnection structure. The substrate comprises a well region of a first conductive type. The first and second gate electrodes are disposed on the substrate. The first, second, and third doped regions are embedded within the well region and are of the first conductive type. The first interconnection structure electrically connects the first gate electrode and the second gate electrode. The first doped region and the second doped region are disposed on opposite sides of the first gate electrode.

Semiconductor device having wide tuning range varactor and method of manufacturing the same

Disclosed is an amplifying circuit and method. In one embodiment, an amplifying circuit, includes: a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein source terminal and body terminal of the first transistor is coupled together through a first resistor.

Method and circuit to isolate body capacitance in semiconductor devices

An integrated circuit includes an inductor that includes a first set of conductors in at least a first metal layer, and a guard ring enclosing the inductor. The guard ring includes a first conductor extending in a first direction, a second conductor extending in a second direction, and a first set of staggered conductors coupled to a first end of the first conductor and a first end of the second conductor. The first set of staggered conductors includes a second set of conductors in a second metal layer, a third set of conductors in a third metal layer and a first set of vias coupling the second set of conductors with the third set of conductors. The third metal layer is above the second metal layer. All metal lines in the second metal layer that are part of the guard ring extend in the first direction.

Integrated circuit with guard ring

A testing system includes: a dividing circuit configured to receive a testing signal and provide a plurality of input signals according to the testing signal; and a plurality of integrated power-amplifiers coupled to the dividing circuit, each of the plurality of integrated power-amplifiers being configured to be tested by receiving a respective input signal of the plurality of input signals and generating a respective output signal for a predetermined testing time.

Power amplifiers testing system and related testing method

A phase shifter includes a first transistor and a second transistor. The first transistor includes a first gate terminal configured to receive a first voltage. The first transistor is configured to adjust at least a resistance or a first capacitance of the phase shifter responsive to the first voltage. The second transistor is coupled to the first transistor. The second transistor includes a second gate terminal configured to receive a second voltage. The second transistor is configured to adjust a second capacitance of the phase shifter responsive to the second voltage. The second gate terminal includes a first polysilicon portion and a second polysilicon portion extending in a first direction. The first polysilicon portion and the second polysilicon portion are positioned along opposite edges of an active region of the first transistor and the second transistor.

Phase shifter circuit, phase shifter layout and method of forming the same

A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

High-implant channel semiconductor device and method for manufacturing the same

A low noise amplifier (LNA) includes a pair of n-type transistors, each configured to provide a first transconductance; a pair of p-type transistors, each configured to provide a second transconductance; a first pair of coupling capacitors, cross-coupled between the pair of n-type transistors, and configured to provide a first boosting coefficient to the first transconductance; and a second pair of coupling capacitors, cross-coupled between the pair of p-type transistors, and configured to provide a second boosting coefficient to the second transconductance, wherein the LNA is configured to use a boosted effective transconductance based on the first and second boosting coefficients, and the first and second transconductances to amplify an input signal.

Wireless receiver

A power amplifier structure includes at least one power amplifier circuit. The power amplifier circuit includes a transistor of a first type connected in series with a transistor of a second type connected between the same voltage supply. In a non-limiting nonexclusive example, an n-type transistor is connected in series with a p-type transistor connected between Vdd. The power amplifier structure can include two amplifier circuits configured in a differential amplifier structure. The differential amplifier structure includes two amplifier circuits operably connected in parallel between the same voltage supply.

Power amplifiers

A band-pass filter (BPF) includes first and second windings. The first winding includes first and second terminals, a first outer extending portion extending from the first terminal, a second outer extending portion extending from the second terminal, and a first conductive structure configured to electrically connect the first and second outer extending portions to each other at a location opposite the first and second terminals. The second winding includes third and fourth terminals positioned between the first and second terminals, and a second conductive structure electrically connected to the third and fourth terminals and extending between the first conductive structure and each of the first and second outer extending portions.

Band-pass filter and method

A semiconductor device is disclosed. The semiconductor device includes a substrate, a transistor, at least one isolation and at least one non-doped region. The substrate includes a lower portion. The transistor is disposed on the lower portion. The at least one isolation is adjacent to the transistor, and disposed on the lower portion. The at least one non-doped region is disposed between and adjacent to the isolation and the lower portion.

An IC includes a device-under-test (DUT) configured to receive a first AC signal at a first node and output a second AC signal at a second node, the second AC signal being based on the first AC signal, and first and second detection circuits. Each of the first and second detection circuits includes a first gain stage coupled to a corresponding one of the first or second nodes through a first capacitive device, a second gain stage in a cascade arrangement with the first gain stage, and a low-pass filter configured to generate a DC signal based on an output signal of the second gain stage.

Test circuit and method

A testing system includes: a dividing circuit configured to receive a testing signal and provide a plurality of input signals according to the testing signal; and a plurality of power-amplifier chips coupled to the dividing circuit, each of the plurality of power-amplifier chips being configured to be tested by receiving a respective input signal of the plurality of input signals and generating a respective output signal for a predetermined testing time.

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Hsinchu, Taiwan

Tzu-Jin Yeh