Taiwan Semiconductor Manufacturing Comp. Ltd.

Tzu-Hua Chiu

Wei-Yang Lee

Chia-Pin Lin

Wei-Han Fan

Po-Yu Lin

Kuan-Hao Cheng

Wei-Min Liu

LI-Li Su

Yee-Chia Yeo

Yuan-Ching Peng

I-Hsieh Wong

Wei Hao Lu

Alex Lee

Po Shao Lin

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The semiconductor device structure includes a gate stack over a top portion of the fin. The semiconductor device structure includes a first nanostructure over the fin and passing through the gate stack. The semiconductor device structure includes a second nanostructure over the first nanostructure and passing through the gate stack. The first nanostructure is thicker than the second nanostructure. The semiconductor device structure includes a stressor structure over the fin and connected to the first nanostructure and the second nanostructure.

Semiconductor device structure and method for forming the same

A semiconductor device includes a base portion on a semiconductor substrate, a channel layer vertically above the base portion and extending parallel to a top surface of the semiconductor substrate, a gate portion between the channel layer and the base portion, a source/drain feature connected to the channel layer, an inner spacer between the source/drain feature and the gate portion, and an air gap between the source/drain feature and the semiconductor substrate. Moreover, a bottom surface of the source/drain feature is exposed in the air gap.

Spacer features for nanosheet-based devices

A semiconductor device and a method of forming the same are provided. In an embodiment, an exemplary semiconductor device includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, and a source/drain feature disposed over the substrate and coupled to the vertical stack of channel members. The source/drain feature is spaced apart from a sidewall of the gate structure by an air gap and a dielectric layer, and the air gap extends into the source/drain feature.

Inner spacer features for multi-gate transistors

A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.

Epitaxial structures exposed in airgaps for semiconductor devices

A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers connected to the source/drain feature, a gate structure between adjacent channel layers and wrapping the channel layers, and an inner spacer between the source/drain feature and the gate structure and between adjacent channel layers. The source/drain feature has a first interface with a first channel layer of the channel layer. The first interface has a convex profile protruding towards the first channel layer.

Devices with improved operational current and reduced leakage current

Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.

Source and drain engineering process for multigate devices

A method of forming a semiconductor including forming a source/drain feature adjacent to a semiconductor layer stack disposed over a substrate. The method further includes forming a dummy fin adjacent to the source/drain feature and adjacent to the semiconductor layer stack. The method further includes performing an etching process from a backside of the substrate to remove a first portion of the dummy fin adjacent to the source/drain feature, thereby forming a first trench in the dummy fin, where the first trench extends from the dummy fin to the source/drain feature. The method further includes forming a first dielectric layer in the first trench and replacing a second portion of the dummy fin with a source/drain contact.

Self-aligning backside contact process and devices thereof

A semiconductor structure is provided. The semiconductor structure includes a first nanostructure stacked over and spaced apart from a second nanostructure, a gate stack wrapping around the first nanostructure and the second nanostructure, a source/drain feature adjoining the first nanostructure and the second nanostructure, and a first inner spacer layer interposing the gate stack and the source/drain feature and interposing the first nanostructure and the second nanostructure. A dopant in the source/drain feature has a first concentration at an interface between the first inner spacer layer and the source/drain feature and a second concentration at a first distance away from the interface. The first concentration is higher than the second concentration.

Growing community of inventors

Hsinchu, Taiwan

Tzu-Hua Chiu