Taiwan Semiconductor Manufacturing Comp. Ltd.

Tzu-Hsuan Hsu

Dun-Nian Yaung

Jen-Cheng Liu

Min-Feng Kao

Ching-Chun Wang

Feng-Chi Hung

Szu-Ying Chen

Jeng-Shyan Lin

Hsiao-Hui Tseng

Wen-De Wang

Shu-Ting Tsai

Chun-Chieh Chuang

Wei-Cheng Hsu

Chun-Ming Su

Shou-Gwo Wuu

Wen-I Hsu

Kuo-Cheng Lee

Chun-Hao Chou

Yung-Lung Hsu

Tsung-Han Tsai

Chin-Min Lin

Ho-Ching Chien

Chung-Yi Yu

Shih Pei Chou

Shih-Pei Chou

Sin-Yao Huang

Chia-Shiung Tsai

Yeur-Luen Tu

Yun-Wei Cheng

Chao-Hsiung Wang

Shyh-Fann Ting

Chien-Hsien Tseng

Tzu-Jui Wang

Yean-Kuen Fang

U-Ting Chen

Han-Chi Liu

Kai-Chun Hsu

Cheng-Hsien Chou

Chen-Jong Wang

Chun-Wei Chang

Yuan-Chih Hsieh

Sheng-Chau Chen

Chih-Yu Lai

Gwo-Yuh Shiau

Cheng-Ying Ho

Alex Hsu

Horng Huei Tseng

Yuichiro Yamashita

Ming Chyi Liu

Shuang-Ji Tsai

Kun-Huei Lin

Chris Hsieh

Horng-Huei Tseng

Shih-Chang Liu

Yen-Yu Chen

Jhy-Jyi Sze

Hsun-Ying Huang

Keng-Yu Chou

Shih-Chi Fu

Shine Chung

Wei-Chieh Chiang

Yen-Ting Chiang

Cheng Yu Huang

Chao-Yang Yeh

Tsung-Hsun Huang

Chung Chien Wang

Yan-Chih Lu

Chi-Hsien Chung

Cheng-Jong Wang

Chen-Hsien Lin

J C Liu

Wen Hao Chang

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor device including a shallow trench isolation (STI) structure disposed between a first side and a second side of the semiconductor substrate. An intermetal dielectric structure comprising a first metal interconnect is on the second side. A first etching process is performed to form a first trench extending from the first side of the semiconductor substrate to the STI structure. A dielectric layer is deposited on the first side. A dielectric material is deposited into the first trench to form a dielectric spacer. A second trench is etched during a second etching process. The second trench is aligned with the first trench and extends through the STI structure to the first metal interconnect. A conductive material is deposited into the second trench to form a contact pad that contacts the first metal interconnect.

Isolation structure for bond pad structure

Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a first chip bonded to a second chip. The first chip includes a semiconductor substrate. The first chip includes a first transistor cell and a second transistor cell. The second transistor cell is laterally spaced from the first transistor cell. A first through-substrate via (TSV) extends vertically through the semiconductor substrate. The first transistor cell is electrically coupled to the first TSV. A second TSV extends vertically through the first semiconductor substrate. The second transistor cell is electrically coupled to the second TSV. The second chip comprises a first readout circuit that is electrically coupled to the first TSV and the second TSV. The first readout circuit is disposed laterally between the first TSV and the second TSV. The first readout circuit is configured to receive a first signal from the first transistor cell.

High-speed readout image sensor

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip including a substrate having an upper surface vertically below a top surface. A dielectric structure contacts the top surface of the substrate. A conductive structure is disposed in the substrate. The conductive structure includes an upper conductive body and conductive protrusions directly underlying the upper conductive body. The upper conductive body overlies the upper surface of the substrate. A bottom surface of the dielectric structure is disposed between a top surface and a bottom surface of the upper conductive body. An isolation structure is disposed in the substrate on opposing sides of the upper conductive body.

Various embodiments of the present disclosure are directed towards an image sensor including a plurality of photodetectors disposed within a substrate. The substrate comprises a front-side surface opposite a back-side surface. An outer isolation structure is disposed in the substrate and laterally surrounds the plurality of photodetectors. The outer isolation structure has a first height. An inner isolation structure is spaced between sidewalls of the outer isolation structure. The inner isolation structure is disposed between adjacent photodetectors in the plurality of photodetectors. The outer isolation structure and the inner isolation structure respectively extend from the back-side surface toward the front-side surface. The inner isolation structure comprises a second height less than the first height.

Isolation structure to increase image sensor performance

The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a substrate having a first side and a second side opposing the first side. The substrate has one or more sidewalls defining a trench extending along opposing sides of a pixel region having a first width. An isolation structure including one or more dielectric materials is disposed within the trench. The isolation structure has a second width. An image sensing element and a focal region are disposed within the pixel region. The focal region is configured to receive incident radiation along the second side of the substrate. A ratio of the second width to the first width is in a range of between approximately 0.1 and approximately 0.2, so that the focal region is completely confined between interior sidewall of the isolation structure facing the image sensing element.

Trench isolation structure for scaled pixel region

A device includes a semiconductor substrate, a gate dielectric over the semiconductor substrate, and a gate electrode over the gate dielectric. The gate electrode has a first portion having a first thickness, and a second portion having a second thickness smaller than the first thickness. The device further includes a source/drain region on a side of the gate electrode with the source/drain region extending into the semiconductor substrate, and a device isolation region. The device isolation region has a part having a sidewall contacting a second sidewall of the source/drain region to form an interface. The interface is overlapped by a joining line of the firs portion and the second portion of the gate electrode.

Gate electrodes with notches and methods for forming the same

Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a photodetector disposed in a semiconductor substrate. An interlayer dielectric (ILD) structure is disposed on a first side of the semiconductor substrate. A storage node is disposed in the semiconductor substrate and spaced from the photodetector, where the storage node is spaced from the first side by a first distance. A first isolation structure is disposed in the semiconductor substrate and between the photodetector and the storage node, where the first isolation structure extends into the semiconductor substrate from a second side of the semiconductor substrate that is opposite the first side, and where the first isolation structure is spaced from the first side by a second distance that is less than the first distance.

Backside illuminated global shutter image sensor

According to one example, a device includes a semiconductor substrate. The device further includes a plurality of color filters disposed above the semiconductor substrate. The device further includes a plurality of micro-lenses disposed above the set of color filters. The device further includes a structure that is configured to block light radiation that is traveling towards a region between adjacent micro-lenses. The structure and the color filters are level at respective top surfaces and bottom surfaces thereof.

Apparatus for reducing optical cross-talk in image sensors

A back side illumination (BSI) image sensor with a dielectric grid opening having a planar lower surface is provided. A pixel sensor is arranged within a semiconductor substrate. A metallic grid is arranged over the pixel sensor and defines a sidewall of a metallic grid opening. A dielectric grid is arranged over the metallic grid and defines a sidewall of the dielectric grid opening. A capping layer is arranged over the metallic grid, and defines the planar lower surface of the dielectric grid opening.

Stacked grid design for improved optical performance and isolation

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a first isolation structure on a first surface of a substrate. A second isolation structure is formed into the first surface of the substrate. Sidewalls of the first isolation structure are disposed laterally between inner sidewalls of the second isolation structure. A bond pad is formed in the substrate such that the second isolation structure continuously laterally wraps around the bond pad.

A device includes a semiconductor substrate, a gate dielectric over the semiconductor substrate, and a gate electrode over the gate dielectric. The gate electrode has a first portion having a first thickness, and a second portion having a second thickness smaller than the first thickness. The device further includes a source/drain region on a side of the gate electrode with the source/drain region extending into the semiconductor substrate, and a device isolation region. The device isolation region has a part having a sidewall contacting a second sidewall of the source/drain region to form an interface. The interface is overlapped by a joining line of the first portion and the second portion of the gate electrode.

A photosensing pixel includes a substrate, a photosensing region, a floating diffusion region, a transfer gate and a control electrode. The photosensing region is located within the substrate. The floating diffusion region is located within the substrate aside the photosensing region. The transfer gate is disposed on the substrate and extending into the photosensing region. The control electrode is located on the substrate and extending into the floating diffusion region.

Photosensing pixel, image sensor and method of fabricating the same

A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the implant isolation region. A gate electrode is disposed over the gate dielectric and an end cap dielectric layer is between the gate dielectric and the gate electrode over the implant isolation region.

Implant isolated devices and method for forming the same

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Kaohsiung, Taiwan

Tzu-Hsuan Hsu