Other

Xintec Corporation

United Microelectronics Corp.

Tzu-Hsiang Hung

Chia-Sheng Lin

Tsang-Yu Liu

Yen-Shih Ho

Bai-Yao Lou

Yu-min Liang

Kun-Ju Li

Po-Cheng Huang

Chien-Hui Chen

Chun-Tsen Lu

Yu-Lung Huang

Yu-Ting Li

Wen-Chin Lin

Chih-Hsun Lin

Chuan-Jin Shiu

Jen-Chieh Lin

Wu-Sian Sie

Hsin-Chih Chiu

Bing-Siang Chen

I-Lun Hung

A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface.

Semiconductor process

An embodiment of the invention provides a chip package which includes a substrate having a first surface and a second surface; a conducting pad structure located on the first surface; a dielectric layer located on the first surface of the substrate and the conducting pad structure, wherein the dielectric layer has an opening exposing a portion of the conducting pad structure; and a cap layer located on the dielectric layer and filled into the opening.

Chip package and method for forming the same

A substrate structure with through vias is provided. The substrate structure with through vias includes a semiconductor substrate having a back surface and a via penetrating the back surface, a metal layer, a first insulating layer and a second insulating layer. The first insulating layer is formed on the back surface of the semiconductor substrate and has an opening connected to the through via. The second insulating layer is formed on the first insulating layer and has a portion extending into the opening and the via to form a trench insulating layer. The bottom of the trench insulating layer is etched back to form a footing portion at the corner of the via. The footing portion has a height less than a total height of the first and second insulating layers.

Substrate structure with through vias

An embodiment of the invention provides a chip package which includes: a substrate; a device region disposed in or on the substrate; a signal pad disposed in or on the substrate and electrically connected to the device region; a ground pad disposed in or on the substrate; a signal bump disposed on a surface of the substrate, wherein the signal bump is electrically connected to the signal pad through a signal conducting layer; a ground conducting layer disposed on the surface of the substrate and electrically connected to the ground pad; and a protection layer disposed on the surface of the substrate, wherein the protection layer completely covers the entire side terminals of the signal conducting layer and partially covers the ground conducting layer such that a side terminal of the ground conducting layer is exposed on a side of the substrate.

An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device disposed at the first surface; a protection layer disposed on the second surface of the substrate, wherein the protection layer has an opening; a conducting bump disposed on the second surface of the substrate and filled in the opening; a conducting layer disposed between the protection layer and the substrate, wherein the conducting layer electrically connects the optoelectronic device to the conducting bump; and a light shielding layer disposed on the protection layer, wherein the light shielding layer does not contact with the conducting bump.

Chip package

A method for forming an image sensor chip package includes: providing a substrate having predetermined scribe lines defined thereon, wherein the predetermined scribe lines define device regions and each of the device regions has at least a device formed therein; disposing a support substrate on a first surface of the substrate; forming at least a spacer layer between the support substrate and the substrate, wherein the spacer layer covers the predetermined scribe lines; forming a package layer on a second surface of the substrate; forming conducting structures on the second surface of the substrate, wherein the conducting structures are electrically connected to the corresponding device in corresponding one of the device regions, respectively; and dicing along the predetermined scribe lines such that the support substrate is removed from the substrate and the substrate is separated into a plurality of individual image sensor chip packages.

Image sensor chip package and method for forming the same

Growing community of inventors

Kaohsiung, Taiwan

Tzu-Hsiang Hung