Taiwan Semiconductor Manufacturing Comp. Ltd.

Tzu-Hen Lin

Yen-Pin Chen

Tai-Yu Cheng

Chung-Hsing Wang

Li-Chun Tien

Lee-Chung Lu

Po-Hsiang Huang

Fong-Yuan Chang

Ting Yu Chen

Chun-Chen Chen

Shao-Huan Wang

Sheng-Hsiung Chen

Florentin Dartu

Wei-Chih Hsieh

Chung-hsing Wang

Sheng-hsiung Chen

An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Integrated circuit having a high cell density

For a method of manufacturing a semiconductor device, a corresponding layout diagram is stored on a non-transitory computer-readable medium, the layout diagram being arranged relative to first and second perpendicular directions, the layout diagram including cells such that, for a subset of the cells, each subject one of the cells (subject cell) in the subset has a neighborhood including first and second neighbor cells on corresponding first and second sides of the subject cell relative to the first direction. The method includes: for each subject cell in the subset, generating a sidefile which represents neighborhood-specific proximity-effect information. For each cell in the subset of the cells, the generating a sidefile includes populating the sidefile with a first neighbor-specific proximity-effect (NSPE) parameter corresponding to an inter-cell proximity-effect induced by the first neighbor cell and a second NSPE parameter corresponding to an inter-cell proximity-effect induced by the second neighbor cell.

Method of generating netlist including proximity-effect-inducer (PEI) parameters

A method for timing optimization is disclosed. The method includes obtaining information on timing of paths in a chip, the information including a mean of slacks and a sigma of slacks of each of the paths; determining a sigma margin (SM) value each of the paths, the SM value being obtained by dividing the mean by the sigma; dividing the paths into groups based on SM values, an SM value of a path in one of the groups being different from that of a path in another one of the groups; and determining a yield requirement that indicates the maximum number of paths allowable in each group in order to achieve a predetermined yield.

Method and system for sigma-based timing optimization

A method for timing optimization is disclosed. The method includes obtaining information on timing of paths in a chip, wherein the information includes a mean of slacks and a sigma of slacks of each of the paths, determining a sigma margin (SM) value each of the paths, the SM value being obtained by dividing the mean by the sigma, and determining that a first path of the paths is more critical than a second path of the paths, an SM value of the first path being smaller than that of the second path.

A method includes identifying the first path as a target path, wherein an operation speed of the target path is adjusted from the corner case; deriving and outputting first values from the lookup table by indexing the lookup table with a threshold voltage associated with the first path identified as the target path as the main threshold voltage and a threshold voltage associated with the second path as the slave threshold voltage; calculating a first extra time based on the first values and first cell delays associated with the first path.

Method of timing analysis

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Hsinchu, Taiwan

Tzu-Hen Lin