Industrial Technology Research Institute

Tzu-Fang Lee

Chien-Hong Lin

Chi-Lung Wang

Jing-Shan Liang

Kuo-Yu Chuang

A configurable processing apparatus includes a plurality of processing units, at least an instruction synchronization control circuit, and at least a configuration memory. Each processing apparatus has a stall-output signal generating circuit to output a stall-output signal, wherein the stall-output signal indicates that an unexpected stall is occurred in the processing unit. The processing unit has a stall-in signal, and an external circuit of the processing unit can control whether the processing unit is stalled according to the stall-in signal. The instruction synchronization control circuit generates the stall-in signals to the processing units in response to a content stored in the configuration memory and the stall-output signals of the processing units, so as to determine operation modes and instruction synchronization of the processing units.

Configurable processing apparatus and system thereof

An image sensor having an output of an integral image is provided. The image sensor includes a pixel circuit, a line accumulator, and a volume accumulator. The pixel circuit includes a plurality of pixels for capturing pixel values of the pixels. The line accumulator is used for accumulating the pixel values of the pixels from a first pixel to a target pixel in a target pixel line of the image so as to obtain an accumulated line pixel value. The volume accumulator is used for adding the accumulated line pixel value output by the line accumulator to an integral pixel value of the pixel corresponding to the target pixel in a previous pixel line of the target pixel line, and using an adding result as the integral pixel value of the target pixel, so as to output the integral pixel value of the target pixel to form an integral image.

Image sensor having output of integral image

A memory device and a refresh method are provided herein. The memory device includes a memory array having memory rows. When an array refresh strobe (ARS) signal is received, it is determined whether the memory rows are required to be refreshed according to tag flags and reset statuses corresponding to the memory rows. When a row refresh strobe (RRS) signal is received, it is determined whether to refresh one of the memory rows according to a plurality of parameters including a value of a row to refresh counter, a value of a refresh deadline counter and/or a queue. When it is decided to start a refresh operation, one of the memory rows is selected according to the tag flag and the status, and the status of the selected memory row is updated after the selected memory row is refreshed.

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Hsinchu, Taiwan

Tzu-Fang Lee