Taiwan Semiconductor Manufacturing Comp. Ltd.

Tzu-Chung Tsai

Chii-Ming M Wu

Jen-Yuan Chang

Hai-Dang Trinh

Yao-Wen Chang

Chia-Ping Lai

Chien-Chang Lee

Cheng-Yuan Tsai

Fa-Shen Jiang

Chia-Hua Lin

Bi-Shen Lee

Fang-yu Liu

Shih-Chang Chen

Hsing-Lien Lin

Eugene I-Chun Chen

Ping-Cheng Ko

Szu-Hsien Lo

Che-Hung Liu

Jhih-Yuan Yang

Julie Yang

Hsun-Chung Kuang

Yen-Chang Chu

Chien-Ying Wu

Tse-Lun Hsu

Jhih-Ming Lin

Yueh Ying Lee

Chii Ming Wu

A semiconductor device includes a first semiconductor die mounted on a substrate, a second semiconductor die mounted on the substrate and separated from the first semiconductor die, a first dielectric material between the first semiconductor die and the second semiconductor die and having a first density, and a column of second dielectric material in the first dielectric material, the second dielectric material having a second density different than the first density, and the second dielectric material including a void region.

Semiconductor device including a plurality of dielectric materials between semiconductor dies and methods of forming the same

An apparatus includes a first portion and a second portion. The first portion includes a first front side wall, a first rear side wall, a top wall, and at least one pivotal pin structure extending from the first rear side wall. The at least one pivotal pin structure comprises a base, a shaft, and a head having a non-circular cross-sectional shape. The second portion includes a second front side wall, a second rear side wall, a bottom wall, and at least one pin holder extending from the second rear side wall. The at least one pin holder defines an opening for accepting the head of the at least one pivotal pin structure at an alignment. The head of the at least one pivotal pin structure extends through the opening. The first portion and the second portion are pivotally movable between an open configuration and a closed container configuration.

Apparatus for storing and transporting semiconductor elements, and method of making the same

An apparatus having a first portion including a first front wall, a first rear wall, and a bottom wall integrally coupled to the first front wall and the first rear wall, and pivotal pin structures integrally coupled to and extending from the first rear wall. The apparatus includes a second portion having a second front wall, a second rear wall, and a top wall integrally coupled to the second front wall and the second rear wall, and pin holders integrally coupled to and extending from the second rear wall and at an offset angle with reference to the top wall. The pivotal pin structure includes a base support connected to the first rear wall and a shaft connected to the base support, and the pin holder defines an opening sized and shaped to accept the shaft. The first and second portions are sized and shaped to be pivotally movable between open and closed configurations.

Semiconductor die carrier structure

A die includes: a semiconductor substrate having a front side and an opposing backside; a dielectric structure including a substrate oxide layer disposed on the front side of the semiconductor substrate and interlayer dielectric (ILD) layers disposed on the substrate oxide layer; an interconnect structure disposed in the dielectric structure; a through-silicon via (TSV) structure extending in a vertical direction from the backside of the semiconductor substrate through the front side of the semiconductor substrate, such that a first end of the TSV structure is disposed in the interconnect structure; and a TSV barrier structure including a barrier line that contacts the first end of the TSV structure, and a first seal ring disposed in the substrate oxide layer and that surrounds the TSV structure in a lateral direction perpendicular to the vertical direction.

Semiconductor die including through substrate via barrier structure and methods for forming the same

A die includes: a semiconductor substrate having a front side and an opposing back side; a dielectric structure including a substrate oxide layer disposed on the front side of the semiconductor substrate and interlayer dielectric (ILD) layers disposed on the substrate oxide layer; an interconnect structure disposed in the dielectric structure; a through-silicon via (TSV) structure extending in a vertical direction from the back side of the semiconductor substrate through the front side of the semiconductor substrate, such that a first end of the TSV structure is disposed in the interconnect structure; and a TSV barrier structure including a barrier line that contacts the first end of the TSV structure, and a first seal ring disposed in the substrate oxide layer and that surrounds the TSV structure in a lateral direction perpendicular to the vertical direction.

A three-dimensional device structure includes a die including a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, a through silicon via (TSV) structure that extends through the semiconductor substrate and electrically contacts a metal feature of the interconnect structure, and an integrated passive device (IPD) embedded in the semiconductor substrate and electrically connected to the TSV structure.

Three-dimensional device structure including substrate-embedded integrated passive device and methods for making the same

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an interconnect structure disposed over a substrate. The interconnect structure includes a plurality of interconnect layers disposed within a dielectric structure. A bond pad structure is disposed over the interconnect structure. The bond pad structure includes a contact layer. A first masking layer including a metal-oxide is disposed over the bond pad structure. The first masking layer has interior sidewalls arranged directly over the bond pad structure to define an opening. A conductive bump is arranged within the opening and on the contact layer.

Film structure for bond pad

Various embodiments of the present disclosure are directed towards a method for forming a memory device. The method includes forming a bottom electrode over a substrate. A data storage structure is formed on the bottom electrode. The data storage structure comprises a first atomic percentage of a first dopant and a second atomic percentage of a second dopant. The first atomic percentage is different from the second atomic percentage. A top electrode is formed on the data storage structure.

Resistive memory cell having a low forming voltage

A method of fabricating a photonic device includes: forming a photonic device structure that includes a SOI substrate, which includes a bulk substrate layer, a buried oxide layer on the bulk substrate layer and an active semiconductor layer on the buried oxide layer; forming an electrically conducting layer in electrical contact of the buried oxide layer, and forming a BEOL structure on a surface of the active silicon layer.

Photonic device on a semiconductor-on-insulator substrate and method of manufacturing thereof

Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A resistor overlies the substrate. The resistor comprises a first metal nitride structure, a second metal nitride structure spaced from the first metal nitride structure, and a metal structure disposed between the first metal nitride structure and the second metal nitride structure. A first dielectric structure is disposed over the substrate and the resistor.

Multi-layered resistor with a tight temperature coefficient of resistance tolerance

Various embodiments of the present disclosure are directed towards an integrated chip. A first conductive structure overlies a substrate. A second conductive structure overlies the first conductive structure. A data storage structure is disposed between the first and second conductive structures. The data storage structure includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. Respective bandgaps of the first, second, and third dielectric layers are different from one another.

Data storage structure for improving memory cell reliability

A three-dimensional device structure includes a first die including a first semiconductor substrate, a second die disposed on the first die and including a second semiconductor substrate, a dielectric encapsulation (DE) layer disposed on the first die and surrounding the second die, a redistribution layer structure disposed on the second die and the DE layer, and an integrated passive device (IPD) embedded in the DE layer and electrically connected to the first die and the redistribution layer structure.

Growing community of inventors

Hsinchu County, Taiwan

Tzu-Chung Tsai