Taiwan Semiconductor Manufacturing Comp. Ltd.

Tzu-Chun Lo

Hua-Tai Lin

Cheng-Cheng Kuo

Shih-Ming Chang

Ching-Che Tsai

Ying-Hao Su

Jeng-Shiun Ho

Ming-Yo Chung

Kuei-Shun Chen

Chia-Chu Liu

Min-Hung Cheng

Hsiao-Wei Su

Chih-Wei Hsu

Hsin-Chang Lee

Tsai-Sheng Gau

Ming-Hsing Tsai

Wen-Chun Huang

Kuei Shun Chen

Jye-Yen Cheng

Ken-Yu Chang

Chih-Hsiang Yao

Chih-Shiang Chou

A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks.

Method for removing semiconductor fins using alternating masks

In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter.

System and method for optimization of an imaged pattern of a semiconductor device

Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.

Method for line stress reduction through dummy shoulder structures

A method of optical proximity correction (OPC) convergence control that includes providing a lithography system having a photomask and an illuminator. The method further includes performing an exposure by the illuminator on the photomask. Also, the method includes optimizing an optical illuminator setting for the lithography system with a defined gate pitch in a first direction in a first template. Additionally, the method includes determining OPC correctors to converge the OPC results with a target edge placement error (EPE) to produce a first OPC setting for the first template. The first OPC setting targets a relatively small EPE and mask error enhancement factor (MEEF)of the defined gate pitch in the first template. In addition, the method includes checking the first OPC setting for a relatively small EPE, MEEF and DOM consistency with the first template of the defined gate pitch in a second, adjacent template.

Optical proximity correction convergence control

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Taipei, Taiwan

Tzu-Chun Lo