Nan Ya Technology Corporation

Nanya Technologies Corporation

N&auml;naya Technology Corporation

Tzu-Ching Tsai

Yi-Nan Chen

Hui Min Mao

Tse-Yao Huang

Hsin-Jung Ho

Lin-Chin Su

Hsien-Wen Liu

Ping Cheng Hsu

Hui-Min Mao

Kaan-Lu Tzou

Shih-Chung Chou

Ying Huan Chuang

Shian-Jyh Lin

Yinan Chen

Chao-Sung Lai

Jengping Lin

Chung-Peng Hao

Hung-Chang Liao

Tse Yao Huang

Liang-Hsin Chen

Frasier Wang

Yu-Pi Lee

I-Sheng Liu

Hung-Hsin Lin

Sheng M Liu

Minn-Jiunn Jiang

Miin-Jiunn Jiang

Jim Wang

Chung Min Lin

The present application provides a deposition system. The deposition system includes a deposition module executing a first deposition recipe on a first wafer to turn a first wafer state of the first wafer to a second wafer state; a first measurement module collecting the second wafer state of the first wafer to generate a first set of data; and an artificial intelligence module coupled to the first measurement module and the etch module, analyzing the first set of data and update the first deposition recipe to a second deposition recipe when the first set of data is not within a predetermined range. The artificial intelligence module is configured for generating the second deposition recipe taking into consideration at least one of a deposition rate of the second wafer, a rate of rotation of the second wafer, and a tilt angle of the second wafer.

Deposition system for fabricating semiconductor device structure

The present application discloses an etching system. The etching system includes an etch module executing a first etching recipe on a first wafer to turn a first wafer state of the first wafer to a second wafer state; a first measurement module collecting the second wafer state of the first wafer to generate a first set of data; and an artificial intelligence module coupled to the first measurement module and the etch module, analyzing the first set of data and update the first etching recipe to a second etching recipe when the first set of data is not within a predetermined range. The artificial intelligence module is configured for generating the second etching recipe taking into consideration at least one of an etching rate of the second wafer, a rate of rotation of the second wafer, and a tilt angle of the second wafer.

Etching system for fabricating semiconductor device structure

The present application discloses a method for controlling an etching tool. The method includes executing a first etching recipe on a current wafer; generating a first set of data of the current wafer by a first measurement module; analyzing the first set of data by an artificial intelligence module coupled to the first measurement module; generating, by the artificial intelligence module, a second etching recipe and applying the second etching recipe to the etching tool when the first set of data is not within a predetermined range; and executing the second etching recipe on a next wafer.

Method for controlling etching tool

The present application discloses a method for controlling a deposition tool. The method includes executing a first deposition recipe on a current wafer; generating a first set of data of the current wafer by a first measurement module; analyzing the first set of data by an artificial intelligence module coupled to the first measurement module; generating, by the artificial intelligence module, a second deposition recipe and applying the second deposition recipe to the deposition tool when the first set of data is not within a predetermined range; and executing the second deposition recipe on a next wafer.

Method for controlling deposition tool

A semiconductor device includes a first composite conductive feature and a second composite conductive feature disposed over a pattern-dense region of a semiconductor substrate. The semiconductor device also includes a third composite conductive feature and a fourth composite conductive feature disposed over a pattern-loose region of the semiconductor substrate. The semiconductor device further includes a dielectric layer disposed over the pattern-dense region and the pattern-loose region of the semiconductor substrate. A first portion of the dielectric layer between the first composite conductive feature and the second composite conductive feature is separated from the semiconductor substrate by an air gap, and a second portion of the dielectric layer between the third composite conductive feature and the fourth composite conductive feature is in direct contact with the semiconductor substrate.

Semiconductor device with composite conductive features and method for preparing the same

The present disclosure provides a semiconductor device with a composite conductive feature and an air gap and a method for preparing the semiconductor device. The semiconductor device includes a first composite conductive feature and a second composite conductive feature disposed over a pattern-dense region of a semiconductor substrate. The semiconductor device also includes a third composite conductive feature and a fourth composite conductive feature disposed over a pattern-loose region of the semiconductor substrate. The semiconductor device further includes a dielectric layer disposed over the pattern-dense region and the pattern-loose region of the semiconductor substrate. A first portion of the dielectric layer between the first composite conductive feature and the second composite conductive feature is separated from the semiconductor substrate by an air gap. A second portion of the dielectric layer between the third composite conductive feature and the fourth composite conductive feature is in direct contact with the semiconductor substrate.

The present application discloses an implanting system. The implanting system includes an etch module executing a first implanting recipe on a first wafer to turn a first wafer state of the first wafer to a second wafer state; a first measurement module collecting the second wafer state of the first wafer to generate a first set of data; and an artificial intelligence module coupled to the first measurement module and the etch module, analyzing the first set of data and update the first implanting recipe to a second implanting recipe when the first set of data is not within a predetermined range. The artificial intelligence module is configured for generating the second implanting recipe taking into consideration at least one of an implanting rate of the second wafer, a rate of rotation of the second wafer, and a tilt angle of the second wafer.

Implanting system for fabricating semiconductor device structure

A circuit device includes: a first substrate having a first barrier layer; a second substrate having a second barrier layer; a first conductive portion arranged over the first barrier layer; a second conductive portion arranged over the second barrier layer; a first expanding pad arranged on the first conductive portion and including a first contact area greater than that of the first conductive portion; and a second expanding pad bonded to the first expanding pad, arranged on the second conductive portion and including a second expanded contact area greater than that of the second conductive portion. The first barrier layer and the second barrier layer include aluminum fluoride.

Method of manufacturing integrated circuit device with bonding structure

The present disclosure provides a semiconductor device with a composite conductive feature and an air gap and a method for preparing the semiconductor device. The semiconductor device includes a first composite conductive feature and a second composite conductive feature disposed over a pattern-dense region of a semiconductor substrate. The semiconductor device also includes a third composite conductive feature and a fourth composite conductive feature disposed over a pattern-loose region of the semiconductor substrate. The semiconductor device further includes a dielectric layer disposed over the pattern-dense region and the pattern-loose region of the semiconductor substrate. A first portion of the dielectric layer between the first composite conductive feature and the second composite conductive feature is separated from the semiconductor substrate by an air gap, and a second portion of the dielectric layer between the third composite conductive feature and the fourth composite conductive feature is in direct contact with the semiconductor substrate.

The present application provides a memory device having a bit line (BL) with a stepped profile. The memory device includes a semiconductor substrate including a first surface; and a bit line disposed on the first surface of the semiconductor substrate, wherein the bit line includes a first dielectric layer, a conductive layer disposed over the first dielectric layer, a second dielectric layer disposed over the conductive layer, and a spacer surrounding the first dielectric layer, the conductive layer and the second dielectric layer, wherein the second dielectric layer includes a first portion surrounded by the spacer, and a second portion disposed over the first portion and exposed through the spacer, wherein a first width of the first portion is substantially greater than a second width of the second portion.

Memory device having bit line with stepped profile

A method for forming an integrated circuit device includes providing a first substrate having a first conductive portion, providing a second substrate having a second conductive portion, performing a first chemical reaction to form a first expanding pad on the first conductive portion to provide a first expanded contact area, performing a second chemical reaction to form a second expanding pad on the second conductive portion to provide a second expanded contact area, and bonding the first substrate to the second substrate with a bonding structure.

Method of forming integrated circuit device with bonding structure

A method for preparing a semiconductor structure includes providing a semiconductor substrate having a first surface; disposing a first dielectric layer over the first surface of the semiconductor substrate, a conductive layer over the first dielectric layer, and a second dielectric layer over the conductive layer; disposing a patterned mask over the second dielectric layer; removing portions of the second dielectric layer, the conductive layer and the first dielectric layer exposed through the patterned mask to form a first trench; forming a spacer surrounding the first dielectric layer, the conductive layer and the second dielectric layer; disposing an energy-decomposable mask over the second dielectric layer and the spacer; irradiating a portion of the energy-decomposable mask by an electromagnetic radiation; removing the portion of the energy-decomposable mask irradiated by the electromagnetic radiation; and removing a portion of the second dielectric layer exposed through the energy-decomposable mask.

Manufacturing method of memory device having bit line with stepped profile

The present disclosure provides a method for preparing a semiconductor device structure. The method includes forming a first metal plug, a second metal plug, a third metal plug, and a fourth metal plug over a semiconductor substrate; forming an energy removable liner covering the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug; performing an etching process to remove a portion of the energy removable layer from the substrate, while remaining an energy removable block between the first metal plug and the second metal plug in the cell region; forming a dielectric layer covering the energy removable block and the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug; performing a thermal treating process to transform the energy removable layer into a first air gap structure including a first air gap enclosed by liner layer.

Method for preparing semiconductor device structure with air gap structure

An integrated circuit device includes a first substrate, a second substrate, a first expanding pad, a second expanding pad and a bonding structure. The first substrate is provided with a first conductive portion, the second substrate is provided with a second conductive portion, the first expanding pad is formed on the first conductive portion to provide a first expanded contact area, the second expanding pad is formed on the second conductive portion to provide a second expanded contact area, and the bonding structure is formed between the first substrate and the second substrate, wherein the first expanding pad is bonded to the second expanding pad.

Integrated circuit device with bonding structure and method of forming the same

The present disclosure provides a semiconductor device structure with an air gap structure and a method for forming the semiconductor device structure. The semiconductor device structure includes a first conductive contact and a second conductive contact disposed over a semiconductor substrate. The semiconductor device structure also includes a first dielectric layer surrounding the first conductive contact and the second conductive contact, and a second dielectric layer disposed over the first conductive contact, the second conductive contact and the first dielectric layer. The first dielectric layer is separated from the semiconductor substrate by a first air gap structure, the first dielectric layer is separated from the second dielectric layer by a second air gap structure, and the air gap structures reduce capacitive coupling between conductive features.

Growing community of inventors

Taoyuan, Taiwan

Tzu-Ching Tsai