Taiwan Semiconductor Manufacturing Comp. Ltd.

Mediatek Corporation

Haynes and Boone, Llp

Tzu-Chin Lin

Ru-Gun Liu

Wen-Chun Huang

Hung-Chun Wang

Chih-Ming Hung

Jeng-Horng Chen

Jui-Lin Hsu

Jing-Hong Conan Zhan

Pei-Shiang Chen

Wei-Hsiu Hsu

Chao-Ching Hung

Nian-Fuh Cheng

Yen-Tso Chen

Jen-Hao Cheng

Faruk Krecinic

Hsiang-Yun Chu

Ping-Chieh Wu

Bao-Chi Peng

Jen-Chieh Lo

Shao-Yun Fang

Chih-Ming Lai

Shih-Ming Chang

Tsong-Hua Ou

Cheng-Hung Chen

Yu-Li Hsueh

Ying-Chou Cheng

Yu-Po Tang

Chia-Chi Lin

Shih-Chi Wang

I-Chang Shih

Hung-Ting Lu

A semiconductor chip includes a first wireless communication circuit, a second wireless communication circuit, and an auxiliary path. The first wireless communication circuit includes a signal path, wherein the signal path includes a signal node. The second wireless communication circuit includes a mixer and a local oscillator (LO) buffer. The LO buffer is arranged to receive and buffer an LO signal, and is further arranged to provide the LO signal to the mixer. The auxiliary path is arranged to electrically connect the LO buffer to the signal node of the signal path, wherein the LO buffer is reused for a loop-back test function of the first wireless communication circuit through the auxiliary path.

Semiconductor chip with local oscillator buffer reused for loop-back test and associated loop-back test method

Concepts and examples pertaining to reconfigurable radio frequency (RF) front end and antenna arrays for radar mode switching are described. A processor associated with a radar system selects a mode of a plurality of modes in which to operate the radar system. The processor then controls the radar system to operate in the selected mode by utilizing a plurality of antennas in a respective configuration of a plurality of configurations of the antennas which corresponds to the selected mode. Each configuration of the plurality of configurations of the antennas results in respective antenna characteristics. Each configuration of the plurality of configurations of the antennas utilizes a respective number of antennas of the plurality of antennas.

Reconfigurable RF front end and antenna arrays for radar mode switching

A system includes a local oscillator (LO) signal generation circuit, a receiver (RX) circuit, and a calibration circuit. The LO signal generation circuit generates an LO signal according to a reference clock, and includes an active oscillator that generates the reference clock. The active oscillator includes at least one active component. The RX circuit generates a processed RX signal by processing an RX input signal according to the LO signal. The calibration circuit checks a signal characteristic of the processed RX signal by detecting if a calibration tone exists within a receiver bandwidth, set a frequency calibration control output in response to the calibration tone being not found in the receiver bandwidth, and output the frequency calibration control output to the LO signal generation circuit. The LO signal generation circuit adjusts an LO frequency of the LO signal in response to the frequency calibration control output.

Apparatus and method for applying frequency calibration to local oscillator signal derived from reference clock output of active oscillator

A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a transmit (TX) function through the auxiliary path.

Semiconductor chip with local oscillator buffer reused for signal transmission and associated transmission method

A wireless system includes an active oscillator and a front-end circuit. The active oscillator is used to generate and output a reference clock. The active oscillator includes at least one active component, and does not include an electromechanical resonator. The front-end circuit is used to process a transmit (TX) signal or a receive (RX) signal according to a local oscillator (LO) signal. The LO signal is derived from the reference clock.

Wireless system having local oscillator signal derived from reference clock output of active oscillator that has no electromechanical resonator

A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a loop-back test function through the auxiliary path.

A wireless system includes a local oscillator (LO) signal generation circuit, a receiver (RX) circuit, and a calibration circuit. The LO signal generation circuit generates an LO signal according to a reference clock. The LO signal generation circuit includes an active oscillator. The active oscillator generates the reference clock, wherein the active oscillator includes at least one active component, and does not include an electromechanical resonator. The RX circuit generates a down-converted RX signal by performing down-conversion upon an RX input signal according to the LO signal. The calibration circuit generates a frequency calibration control output according to a signal characteristic of the down-converted RX signal, and outputs the frequency calibration control output to the LO signal generation circuit. The LO signal generation circuit adjusts an LO frequency of the LO signal in response to the frequency calibration control output.

Apparatus and method for applying frequency calibration to local oscillator signal derived from reference clock output of active oscillator that has no electromechanical resonator

The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table.

Electron beam data storage system and method for high volume manufacturing

A method and computer program are provided for analyzing a set of layers within an integrated circuit design to determine a set of critical points for each layer within the set of layers. The critical points are based at least in part on manufacturer specific process parameters. The method includes assigning a critical point value to each of the critical points within each set of critical points, analyzing a path through the integrated circuit design across multiple integrated circuit design layers, and determining a sum of critical point values of each critical point along the path.

Chip level critical point analysis with manufacturer specific data

The present disclosure relates to a method and apparatus to create a physical layout for electron-beam lithography, comprising defining a layout grid for a physical design, the layout grid further comprising vertical grid lines which coincide with stitching lines resulting from partitioning the physical design into a plurality of subfields. The physical design is assembled in accordance with design restrictions regarding interaction between design shapes and the layout grid. In some embodiments, the design restrictions are realized though layout restrictions. In some embodiments, the design restrictions are realized by shifting standard cells to minimize design shape interaction with the layout grid in a post-layout step. In some embodiments, the design restrictions are realized by exchanging positions between a plurality of standard cells for an exchange permutation which minimizes the number of interactions in a post-layout step. In some embodiments a routing grid is refined to rule out interactions between a subset of design constructs and the layout grid. Remaining design shape placement is then optimized along the routing grid relative to the stitching lines.

Layout design for electron-beam high volume manufacturing

The present disclosure describes a method of calibrating a contour. The method includes designing an anchor pattern, printing the anchor pattern on a substrate, collecting scanning electron microscope (SEM) data of the printed anchor pattern on the substrate, wherein the SEM data includes a SEM image of the printed anchor pattern on the substrate, converting the SEM image of the printed anchor pattern on the substrate into a SEM contour of the printed anchor pattern, analyzing the SEM contour of the printed anchor pattern, and aligning the SEM contour of the anchor pattern to form the calibrated SEM contour.

Contour alignment system

A method of designing an IC design layout having similar patterns filled with a plurality of indistinguishable dummy features, in a way to distinguish all the patterns, and an IC design layout so designed. To distinguish each pattern in the layout, deviations in size and/or position from some predetermined equilibrium values are encoded into a set of selected dummy features in each pattern at the time of creating dummy features during the design stage. By identifying such encoded dummy features and measuring the deviations from image information provided by, for example, a SEM picture of a wafer or photomask, the corresponding pattern can be located in the IC layout. For quicker and easier identification of the encoded dummy features from a given pattern, a set of predetermined anchor dummy features may be used.

Distinguishable IC patterns with encoded information

Provided is a method of performing a maskless lithography process. The method includes providing a proximity correction pattern. The method includes generating a deformed pattern based on the proximity correction pattern. The method includes performing a first convolution process to the proximity correction pattern to generate a first proximity correction pattern contour. The method includes processing the first proximity correction pattern contour to generate a second proximity correction pattern contour. The method includes performing a second convolution process to the deformed pattern to generate a first deformed pattern contour. The method includes processing the first deformed pattern contour to generate a second deformed pattern contour. The method includes identifying mismatches between the second proximity correction pattern contour and the second deformed pattern contour. The method includes determining whether the deformed pattern is lithography-ready in response to the identifying.

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Hsinchu, Taiwan

Tzu-Chin Lin