Novatek Microelectronics Corp.

Realtek Semiconductor Inc.

Tzu-Chien Tzeng

Ju-Lin Huang

Chao-Cheng Lee

Chun-Yu Lin

Shen-Iuan Liu

Keko-Chun Liang

Ming-Dou Ker

Jie-Ting Chen

Yu-Pin Chou

Che-Wei Yeh

Yu-Hsiang Wang

Tzuo-Bo Lin

An-Ming Lee

Po-Hsiang Fang

Tay-Her Tsaur

Chieh-An Lin

Jian Liu

Jin-Yi Lin

Yong-Ren Fang

Federico Agustin Altolaguirre

Kuo-Sheng Huang

Cheng-En Hsieh

Rong-Kun Chang

Ping-Chang Lin

Hung-Yi Cheng

Chang-Cheng Huang

A differential input circuit and a driving circuit including the same are provided. The differential input circuit transforms an analog voltage signal corresponding to a sensing line on an OLED panel to a pair of differential input signals being output to a gain amplifier. The differential input circuit includes a sampling circuit and a scaling circuit. The sampling circuit receives the analog voltage signal and a reference voltage through a first scaling path and a second scaling path, respectively. The scaling circuit includes a first scaling path and a second scaling path. The first scaling path and the second scaling path collectively generate the pair of differential input signals, based on a first shift voltage, a first scaled voltage, a second shift voltage, and a second scaled voltage. The first shift voltage is less than the second shift voltage.

Differential input circuit and driving circuit

The disclosure provides a sensing apparatus and an operation method thereof. The sensing apparatus includes a sensing circuit, an analog-to-digital converter (ADC) circuit, a disturbing circuit and an output circuit. The sensing circuit is configured to output a sensing signal indicating a sensing result of a sensing line of the display panel. The ADC circuit is coupled to the sensing circuit to receive the sensing signal and outputs sensing data related to the sensing signal. The disturbing circuit is coupled to the ADC circuit to receive the sensing data and generates a time-variant disturbance component to disturb the sensing data to generate disturbed data. The output circuit is coupled to the disturbing circuit to receive the disturbed data.

Sensing apparatus for display panel and operation method thereof

A reference voltage generator includes a detecting voltage provider, a comparator, and a core circuit. The detecting voltage provider provides a detecting voltage with a first voltage level corresponding to a voltage coefficient. The comparator compares the first voltage level of the detecting voltage with a plurality of sampled amplitudes of an input signal to respectively generate a plurality of comparison results. The core circuit is used to: collect a plurality of first comparison results associated with a current received bit of a preset value from the comparison results; take the voltage coefficient as a first boundary voltage coefficient in response to the first comparison results satisfying a first condition; take the voltage coefficient as a second boundary voltage coefficient in response to the first comparison results satisfying a second condition. The reference circuit generates a reference voltage according to the first and second boundary voltage coefficients.

Reference voltage generator

A dynamic amplifier includes a first output capacitor, a first switch, a current source, a second switch, a voltage detector, a third switch and a level shifter. The first switch is coupled between a first terminal of the first output capacitor and a voltage detection node. The second switch is coupled to the current source and the voltage detection node. The voltage detector is coupled to the voltage detection node and the first switch. The third switch is coupled between the voltage detection node and a power source. The level shifter is coupled to a second terminal of the first output capacitor.

Dynamic amplifier and related gain boosting method

An electrostatic discharge (ESD) protection device and an operation method of the ESD protection device are provided. The ESD protection device includes an ESD current rail, an ESD protection element string, and a bias circuit. A first end and a second end of the ESD protection element string are electrically connected to the ESD current rail and a signal pad, respectively. The ESD protection element string includes a first ESD protection element and a second ESD protection element that are serially connected. The bias circuit is electrically connected to the ESD protection element string to provide a bias voltage to a common connection node between the first ESD protection element and the second ESD protection element.

Device and operation method for electrostatic discharge protection

A clock and data recovery circuit with jitter tolerance enhancement is provided. The CDR circuit includes: a bang-bang phase detector, a digital filter, a digitally controlled oscillator, and an adaptive loop gain control circuit. The CDR circuit detects a loop bandwidth variation and adjusts the loop bandwidth of CDR circuit by adjusting proportional path and integral path gain factors of the digital filter of the CDR circuit. The loop gain controller uses two methods to adjust the loop gain in CDR circuit: bang-bang adjusting method and linear adjusting method.

Clock and data recovery circuit with jitter tolerance enhancement

In the disclosure, an electrostatic discharge (ESD) protection circuit is coupled between a first power rail and a second power rail to discharge any ESD stress. The ESD protection circuit includes a detection circuit, a triggering circuit, and a dual silicon controlled rectifier (DSCR) device. When an ESD stresses is being applied to the first or second power rail, the detection circuit may first detect the ESD stresses and output a detection signal to the triggering circuit. The triggering circuit generates a triggering signal based on the detection signal and the polarity of the ESD stress. Then, the DSCR device is symmetrically triggered based on the triggering signal received at a common node between at least two transistors of the same type. The exemplary ESD protection circuit may be implemented in nanoscale manufactured integrated circuit and achieve good ESD robustness while maintaining low standby leakage current and relatively small silicon footprint.

Electrostatic discharge protection circuit

A silicon controlled rectifier including a semiconductor substrate, first and second semiconductor wells, first and second semiconductor regions, third and fourth semiconductor regions and a silicide layer is provided. The first and the second semiconductor wells are formed in the semiconductor substrate. The first and the second semiconductor regions are respectively formed in the first and the second semiconductor wells in spaced apart relation. The third and the fourth semiconductor regions are respectively formed in the first and the second semiconductor wells. The silicide layer is formed on the third and the fourth semiconductor regions. The silicon controlled rectifier is at least suitable for high frequency circuit application. The silicon controlled rectifier has a relatively low trigger voltage, a relatively high electrostatic discharge level, and a relatively low capacitance.

Silicon controlled rectifier

An electronic static discharge protection apparatus provided. A plurality of ESD circuits serially coupled between a pad and a internal circuit, a first stage ESD circuit includes a ESD element directly coupled to the pad, and a last stage ESD circuit includes an inductive element directly coupled to the internal circuit, so as to improve electronic discharge protecting ability of the ESD protection apparatus and increase circuit operation bandwidth without signal loss attenuation.

Electrostatic discharge protection apparatus

A control method utilized in a clock data recovery device supporting a plurality of frequency bands, for controlling the clock data recovery device to select an operating frequency band from the plurality of frequency bands and to generate a recovery clock for generating retimed data, includes receiving a serial data stream with a data frequency; making each frequency band of the plurality of frequency bands correspond to a plurality of frequency band groups, wherein each frequency band group includes at least one frequency band and corresponds to different frequency ranges; selecting a frequency band group from the plurality of frequency band groups as a coarse-tuned frequency band group according to the data frequency and a locking voltage range; and selecting a frequency band from the plurality of frequency bands according to the data frequency, the locking voltage range and the coarse-tuned frequency band group for generating the recovery clock.

Control method for selecting frequency band and related clock data recovery device

A jitter generator for generating a jittered clock signal, includes a jitter control signal generator and a jittered clock generator. The jitter control signal generator is utilized for selecting a digital control code from a plurality of candidate digital control codes at individual time points and respectively outputting a plurality of selected digital control codes. The jittered clock generator is coupled to the jitter control signal generator, and utilized for generating the jittered clock signal. The jittered clock generator dynamically adjusts the jittered clock signal according to the plurality of different digital control codes.

Jitter generator for generating jittered clock signal

An equalizer and a related equalizing method for equalizing signal reflection caused by a stub at a transmitting end are provided. The equalizer includes a summing device and a delay device. The summing device is utilized for adding a feedback delay signal to the input signal to generate the equalized signal. The delay device is coupled to the summing device, and utilized for delaying the equalized signal to generate the feedback delay signal. Wherein the delay device has a variable delay time and the variable delay time is a non-integer multiple of a bit time of the input signal.

Equalizer and equalizing method

A clock and data recovery circuit includes a voltage controlled oscillator for generating an output clock according to a control voltage signal, a loop filter for outputting the control voltage signal according to a current output, a charge pump unit for outputting the current output according to an error signal, and a controller for determining a run length corresponding to input data based on the output clock from the voltage controlled oscillator. The controller further controls at least one of the voltage controlled oscillator, the loop filter and the charge pump unit according to the run length to dynamically adjust loop bandwidth. A method of adjusting loop bandwidth is also disclosed.

Clock and data recovery circuit

The present invention discloses a signal receiving method for determining a transmission format of an input signal and a related signal receiving circuit. The signal receiving method includes: receiving the input signal; generating a signal detecting result corresponding to at least a signal transmission channel of a plurality of signal transmission channels according to an output result of the signal transmission channel; and determining the transmission format of the input signal according to the signal detecting result. The signal receiving circuit includes: an input interface, for receiving an input signal; a detecting module, for generating a signal detecting result corresponding to at least a signal transmission channel of a plurality of signal transmission channels according to an output result of the signal transmission channel; and a determining unit, for determining the transmission format of the input signal according to the signal detecting result.

Signal receiving method for determining transmission format of input signal and related signal receiving circuit

A leakage current suppressing circuit includes a bias generating unit and a switch unit. The bias generating unit is adapted to be coupled to a power source and an output terminal, and generates a bias voltage substantially equal to a voltage at the power source when the power source is turned on, and substantially equal to a voltage at the output terminal when the power source is turned off. The switch unit includes a first P-type transistor having a first terminal adapted to be coupled to the power source, a second terminal adapted to be coupled to the output terminal, a gate terminal, and a body terminal coupled to the bias generating unit for receiving the bias voltage therefrom.

Growing community of inventors

Hsinchu, Taiwan

Tzu-Chien Tzeng