Cirrus Logic Inc.

Genesis Microchip Corporation

Chips and Technologies, Llc.

Genesis Microchip (delaware) Inc.

Tzoyao Chan

Jih-Hsien Soong

Chih-Ta Sung

Chia-Lun Hang

Richard Chang

Yuanyuan Sun

Alexander Julian Eglit

Osamu Kobayashi

Ali Noorbakhsh

John Lattanzi

Daniel Thomas Daum

Jeffrey G Ort

Mark A Rosenau

Ramaswamy Prabhakar

Milton Cheung

Hongjun Shu

Vincent W Wang

Keys (e.g., decryption key, authentication key) are stored in a non-volatile memory of a display unit. The keys are retrieved in encrypted form into an integrated circuit. The integrated circuit decrypts the keys and uses the keys. As the keys are available in decrypted form only within the integrated circuit and potentially only during use, the keys may not be available to unauthorized third parties.

Display unit storing and using a cryptography key

A monolithic integrated circuit for use in a digital display unit. The circuit may include an analog-to-digital converter (ADC), a scaler and a clock recovery circuit. The present invention enables the integration of at least these components into a single monolithic integrated circuit while maintaining reasonable display quality. Specifically, the monolithic integrated circuit is designed for substantial immunity from noise, which may otherwise result from integration.

Monolithic integrated circuit implemented in a digital display unit for generating digital data elements from an analog display signal received at high frequencies

A multimedia system includes an audio/video decompresser/decoder for decompressing/decoding a compressed/encoded audio/video data stream in order to generate video images for display on a display device and to generate audio signals for audible reproduction. The multimedia system includes an integrated system and video decoder that has a novel memory controller and a novel method for displaying complete decoded/decompressed video frames on a display device without tearing. By use of selective storage of decoded/decompressed video frames in memory, tearing is prevented but information for predicting motion of a video segment is preserved.

Memory controller for decoding a compressed/encoded video data frame

A circuit and method for increasing the processing efficiency of texture map data requests within a 3D subunit of a computer controlled graphics display system. The 3D graphics display subsystem includes a polygon engine, a texture map engine and a pixel pipeline. The texture map engine contains a texture map data access (TDA) circuit having a cache controller with a computer readable cache memory for containing recently used texture maps stored in (u,v) coordinate space. The cache controller is limited in handling only n cache miss operations simultaneously. In one embodiment, n is 1. The TDA circuit also contains a texture map address (TMA) FIFO memory unit for storing texture map addresses associated with texture data requests that hit or missed in the cache memory unit. Since the cache controller handles up to n misses, the texture engine stalls when the (n+1).sup.th unprocessed texture request miss is encountered. Therefore, the TMA FIFO at any time contains at most n miss addresses therein. Processing efficiency is increased when a miss is encountered but the TMA FIFO contains unprocessed hit addresses. At this time, simultaneously with the cache controller fetching the texture data for the missed address, it can also advantageously: (1) supply data from the cache memory for the previously encountered and stored hit addresses; and (2) accept new hit addresses into the TMA FIFO thereby effectively avoiding a texture engine stall. This is quite unlike the prior art systems which process no hit addresses upon a texture miss but rather stall the texture engine.

Enhanced texture map data fetching circuit and method

A decoder is disclosed for decoding MPEG video bitstreams encoded in any color space encoding format and outputting the decoded video bitstream to different sized windows. Both MPEG decompression and color space decoding and conversion are performed on the bitstreams within the same decoder. The disclosed decoder may be programmed to output the decoded video bitstream in any of three primary color space formats comprising YUV 4:2:0, YUV 4:2:2, and YUV 4:4:4. The decoder may also output the decoded bitstream to different sized windows using Discrete Cosine Transform (DCT) based image resizing.

Universal MPEG decoder with scalable picture size

A multimedia system including an audio/video decoder/decompresser for decoding/decompressing a compressed encoded audio/video data stream to generate video images for display and audio signals for audible reproduction. The multimedia system includes an integrated system and video decoder with an audio/video synchronization circuit for substantially synchronizing the display of video images with audio playback. In addition, a step control is provided to allow for viewing of video images on a frame-by frame basis or to freeze or play video in slow motion. When step control is activated, audio output is muted. Audio data corresponding to displayed video is transmitted to the muted audio decoder. An internal system clock may be suppressed to the system clock counter. An external CPU may provide system clock start times corresponding to video frames to be displayed. The external CPU may increment the system clock counter by a an amount corresponding to the difference between a successive frame or number of frames. When nominal playback is resumes, the audio and video data streams are substantially in synchronization.

Stream synchronization method and apparatus for MPEG playback system

An automatic bus identification circuit is provided in a device to reliably detect system bus type on power up despite fluctuations in supply voltage. A system bus type signal is received over a multi-function input line at a first input and a reset signal received over a set line at a second input. A bus type identification circuitry is provided to latch the system bus type signal upon power up and continuously output this signal as a system bus type identification signal. To prevent the influence of disturbances in the power supply upon power-up, a flip-flip is provided to output a logic signal in response to a system reset signal. The flip-flop is configured with a strong-N type inverter to insure that the flip-flop will be set into a grounded state as power is applied to the circuit, despite the influence of transient power supply voltages.

Reset based computer bus identification method and circuit resilient to

A multimedia system including an audio/video decoder/decompresser for decoding/decompressing a compressed encoded audio/video data stream to generate video images for display and audio signals for audible reproduction. The multimedia system includes an integrated system and video decoder with an audio/video synchronization circuit for substancially synchronizing the display of video images with audio playback. A method is described for detecting when the playback of audio and the display of video images are out of synchronization. The circuitry includes three programmable registers, a finite state machine and one full adder using an audio presentation time stamp and the video presentation time stamp. The method uses a rounded programmable bias value which is compared with the difference between the video presentation time stamp and the audio presentation time stamps. The difference may included the latency delay of the audio and video display devices to more properly reflect the synchronization status between audio and video. The circuit area used by the circuitry has been minimized by selective rounding or truncation of the audio presentation time stamp and the video presentation time stamp without sacrificing the accuracy or speed of determining the synchronization between audio and video.

Programmable audio-video synchronization method and apparatus for

A cache controller with both burst and hidden refresh modes. In the burst mode, refresh requests are counted, but not acted on, until a predetermined number of refresh requests have been received. At that time, multiple refreshes are done in a single sequence. Although the amount of time taken for actually refreshing the memory is the same, the time needed for arbitration to obtain control of the necessary busses is reduced, giving an overall savings of time. In the hidden refresh mode, a refresh is done, but no hold signal is sent back to stop the CPU while the refresh is being done. Circuitry is provided which allows local memory accesses, but holds other memory accesses until the refresh is completed. Thus, local memory accesses, which expect data quickly, are not inhibited and other memory accesses, which the CPU expects may take some time, can be held up without the CPU knowing.

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Saratoga, CA, United States of America

Tzoyao Chan