Himax Technologies, Inc.

Chimei Innolux Corporation

Chi Mei Optoelectronics Corporation

Tzong-Yau Ku

Lin-Kai Bu

Ying-Lieh Chen

Chien-Ru Chen

Chin-Tien Chang

Yung-Yu Tsai

Bou-Herng Hwei

In a display driver, image data are assembled with synchronization information to form a stream of digital data. The stream of digital data is transmitted from a timing controller to a data driver along with a timing signal having phase-delayed pulses obtained from an external clock received by the timing controller. In response to the timing signal, the data driver can extract a synchronizing signal from the synchronization information embedded in the stream of digital data, and use the synchronizing signal for generating an internal clock signal. Encoded image data in the stream of digital data then can be retrieved according to the internal clock signal.

System and method for handling image data transfer in a display driver

A wafer and a test method thereof are provided. The invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.

Wafer and test method thereof

A driving circuit of a flat panel display device includes a horizontal bus, a plurality of horizontal driver ICs, a vertical bus, and a plurality of vertical driver ICs. The horizontal driver IC is operative to decode N-types of vertical driving signals output from the horizontal bus, so as to transmit the N-type vertical driving signals to the corresponding vertical driver IC via a vertical signal line of the vertical bus.

Driving circuit of flat panel display device

A chip-on-glass panel device includes a glass substrate having a pixel area, an integrated circuit area, and a fan out area, the fan out area located between the pixel area and the IC area, a plurality of integrated circuit devices arranged within the integrated area of the glass substrate, each of the plurality of integrated circuit devices have an active surface, a plurality of output pads, each arranged on the active surface, and a plurality of signal pads/gamma pads, each arranged on the active surface, and a plurality of signal wires/gamma wires, each having a curved shape geometry and disposed within the fan out area, for connecting the plurality of signal pads/gamma pads of adjacent ones of the plurality of integrated circuit devices through the fan out area.

Chip-on-glass panel device

A level shift circuit includes: a first transistor coupled to a first reference voltage for receiving a first voltage input signal; a second transistor coupled to a second reference voltage; a first diode-connected transistor coupled between the second transistor and the first diode-connected transistor; a third transistor coupled to the first reference voltage and the second transistor, for receiving a second voltage input signal, wherein the first voltage input signal is an inverse version of the second voltage input signal; a fourth transistor coupled to the second reference voltage and the first transistor; a second diode-connected transistor coupled between the fourth transistor and the third transistor; and a fifth transistor coupled to the second voltage input signal, the first reference voltage, and the fourth transistor, wherein a level-shifted output signal corresponding to the first voltage input signal is generated at an output node of the fourth transistor.

Level shift circuit

A wafer, a test system thereof, a test method thereof and a test device thereof are provided. The present invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.

Wafer test system wherein period of high voltage stress test of one chip overlaps period of function test of other chip

A display includes an array of pixel circuits and data drivers to drive the pixel circuits. The data drivers include a first data driver to receive pixel data according to a first clock frequency and to forward some of the pixel data to a second data driver according to a second clock frequency, the second clock frequency being different from the first clock frequency.

Growing community of inventors

Tainan County, Taiwan

Tzong-Yau Ku