Integrated Device Technology, Inc.

Tzong-Kwang (Henry) Yeh

Casey E Springer

Jiann-Jeng (John) Duh

A synchronous memory system configurable in a multiplexed or non-multiplexed mode. In the multiplexed mode, address and data are provided on a shared bus, and accesses to the memory system are qualified by memory access control signals, including an address strobe signal, a counter enable signal and a counter repeat signal. A read/write control signal is maintained for one cycle after the last valid access command to avoid bus turn-around problems. In the multiplexed mode, chip enable and output enable signals may be constantly activated, thereby simplifying associated printed circuit board design. Different ports of the synchronous memory system can be independently configured to operate in either the multiplexed or non-multiplexed mode.

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Palo Alto, CA, United States of America

Tzong-Kwang (Henry) Yeh