National Science Council

Tzong-Bang Yu

Shen-Iuan Liu

Hen-Wai Tsao

A direct digital frequency synthesizer outputting a sine signal is disclosed, comprising an accumulator, a symmetry circuit, a coarse circuit, a fine circuit and a sign circuit, wherein the accumulator sequentially outputs a sample address according to a frequency control signal. The symmetry circuit takes the complement of the sample address according to a first clock, the period of the first clock being twice the period of the first MSB of the sample address, to obtain a symmetric sample address represented by N bits. The coarse circuit connected to the symmetry circuit outputs the first M MSBs of the symmetric sample address as the first M MSBs of the sine signal. The fine circuit predicts the last N-M LSBs of the sine signal from the last N-M LSBs of the symmetric sample address according to the first M MSBs of the symmetric sample address of the coarse circuit. Then, the sign circuit outputs a sign bit of the sine signal according to a second clock, the period of the second clock being four times that of the period of the first MSB of the symmetric sample address.

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Yi-Lan Hsien, Taiwan

Tzong-Bang Yu