Vanguard International Semiconductor Corporation

Broadcom Corporation

Chrontel International Ltd.

Tzi-Hsiung Shu

Sunetra K Mendis

An improved slicer for a data receiver is described. In particular, an improved slicer architecture with improved noise immunity and improved tolerance to signal level shift of an input signal to the data receiver is disclosed. The improvement is achieved through using multiple comparators to account for a wider range of the noise and input signal level shift. Other methods and apparatuses are described therein, including a two-comparator and a four comparator embodiments.

Method and apparatus for improved input data slicer

An apparatus, method, and system for DC offset cancellation are provided herein. For instance, the apparatus can include a first commutating mixer switch and a second commutating mixer switch. The first commutating mixer switch can have a first input port configured to receive a first differential signal and a first differential output port. The second commutating mixer switch can have a second input port configured to receive a second differential offset signal and a second differential output port. The first and second differential output ports can be coupled to one another to provide a combined differential output signal.

DC offset calibration for a radio transceiver mixer

A mixer for a radio transceiver includes a commutating mixer switch having a first differential input port coupled to a DC offset cancellation path. The first differential input port of the mixer switch includes a first terminal coupled to a first end of a first resistor and a second terminal coupled to a first end of a second resistor. Second ends of the first and second resistors are configured to receive a differential input signal. The DC offset cancellation path may provide a resistively coupled DC calibration signal for reducing the magnitude of DC offsets that may be present at the input of the mixer switch. The concept can be used for either image or non-image reject mixers.

Effectively defect free images are obtained from CMOS image sensors through a two step method in which the addresses of bad pixels are recorded during sensor testing and stored in an on-chip directory. Then, during sensor readout, each pixel address is checked to determine if it represents that of a bad pixel. If this is determined to be the case, the bad pixel value is replaced by another value. This replacement value is generated from an average of the nearest-neighbors that are not defective. If testing is performed at the wafer level, said bad pixel and nearest neighbor data may be used to modify the final level wiring so that bad pixels are disconnected and replaced by their nearest neighbors.

Pixel defect correction in a CMOS active pixel image sensor

The invention provides a method and apparatus for reducing image lag in CMOS active pixel sensors at low light levels by controlling the reset level. By ensuring that the reset level is independent of the preceding signal level, the problem of image lag can be avoided. Always resetting a photodiode to a fixed voltage is a hard reset. The maximum signal swing is limited by the reset level and the column readout amplifier. If the column circuits are not modified, using hard reset can reduce the maximum signal swing. However in dark images only a portion of the full scale is used. Therefore the amplifier gain setting can be used to determine whether to use a hard reset or soft reset. This method and apparatus for using hard or soft reset dependent on signal level improves image quality at low light levels without compromising performance at high illumination.

Method and apparatus of controlling a pixel reset level for reducing an image lag in a CMOS sensor

Apparatus and methods for testing an active pixel sensor ensure that a signal proportional to the quantity of light energy impinging on the active pixel sensor is reliably and accurately captured and made available for further on processing the rest of the APS system circuitry. The apparatus and method determines the capacitance of a photo-conversion device of the active pixel sensor. The apparatus and method determines that an active pixel sensor is functioning correctly. The apparatus and method determines the performance of an active pixel sensor. Where the performance of the active pixel sensor is a measure of linearity of the active pixel sensor and a connected chain of circuitry that process the signal converted by the photo-conversion device of the active pixel sensor.

On-chip design-for-testing structure for CMOS APS (active pixel sensor) image sensor

A duty cycle correcting circuit is described having a first capacitor connected between a first node and a reference node and a second capacitor connected between a second node and the reference node. When the duty cycle of the output clock signal is greater than 50% the voltage across the second capacitor decreases thereby increasing the charging rate of the first capacitor, decreasing the discharging rate of the first capacitor, and restoring the output duty cycle to 50%. When the duty cycle of the output clock signal is less than 50% the voltage across the second capacitor increases thereby decreasing the charging rate of the first capacitor, increasing the discharging rate of the first capacitor, any restoring output duty cycle to 50%.

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San Jose, CA, United States of America

Tzi-Hsiung Shu