Macronix International Co., Ltd.

Chingis Technology Corporation

Tzeng-Huei Shiau

Ray-Lin Wan

Yu-Shen Lin

Chun-Hsiung Hung

Han-Sung Chen

Fuchia Shone

I-Long Lee

Yuan-Chang Liu

Kuen-Long Chang

Hsien-Wen Liu

Tom D Yiu

Chun Hsiung Hung

Ray L Wan

Han Sung Chen

Shang-De Chang

Weitong Chuang

Alex Wang

Han-Chih Lin

I-Sheng Liu

Tso-Ming Chang

Chung-Kuang Chen

Wen-Pin Lu

Chun-Jen Huang

Yung Feng Lin

Chia-Shing Chen

Yao-Wu Cheng

Fu-Chia Shone

Jin-Lien Lin

Yu-Sui Lee

Chung-Cheng Tsai

Hun-Song Chen

Caiyun Wu

Qifang Wang

Kong Mou Liou

A capacitor string structure, a memory device and a charge pump circuit thereof are provided. The capacitor string structure includes a plurality of conductive plates. The conductive plates are disposed in the memory device. The conductive plates are stacked to each other, and respectively form a plurality of word lines of the memory device, where two neighbored conductive plates form a capacitor.

Capacitor string structure, memory device and electronic device

In one aspect, a first charge pump has serially arranged charge pump stages. Inter-stage nodes between adjacent stages are pumped by a second charge pump. In another aspect, timing of the charge pump stages is controlled by at a command clock signal. The command clock signal and command data are communicated between a integrated circuit with the charge pump and an external circuit.

Charge pump system

A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly two-transitor PMOS memory cell for one-time programming applications includes a PMOS floating gate transistor having a source formed as a p+ diffusion region in a single n-well. The source is adapted to also serve as control plate for the floating gate transistor.

Nonvolatile memory solution using single-poly pFlash technology

A method and an integrated circuit for performing a soft program after erase provides efficient convergence of over-erased floating gate memory cells disposed in bit lines. The soft program is applied to successive subject bit lines. The BLISP method includes selection of a selected bit line and applying the soft program to a subject bit line corresponding to the selected bit line. For integrated circuits having no defective bit lines, the subject bit lines comprise the selected bit lines. The BLISP method is adapted for low current consumption compared to bulk soft programming methods. In some embodiments, the integrated circuit includes defective bit lines. For these integrated circuits, the selection of the selected bit line includes indicating a bit line type corresponding to the selected bit line. The defective bit lines are logically replaced by redundant bit lines so that the soft program is applied to conforming selected bit lines and redundant bit lines corresponding to defective bit lines. The defective bit lines in the first memory array can be disabled during the soft program and replaced by corresponding redundant bit lines disposed in the second memory array, so that the soft program is not applied to the defective bit lines. By preventing application of the soft program to the defective bit lines, the BLISP method avoids consumption of excessive current that would otherwise be consumed by very low threshold voltage memory cells disposed on the defective bit lines. The excessive current would render the soft program method much less efficient.

Method and integrated circuit for bit line soft programming (BLISP)

A circuit is provided for applying a negative voltage to the control gate of a floating gate memory cell and a positive voltage to the source drain or channel which comprises a positive voltage source to provide a positive voltage to the source of the cell, and a negative voltage source responsive to the supply voltage to provide a negative voltage to the control gate. A voltage regulator is included that is coupled to the negative voltage source and to the positive voltage source to maintain the negative voltage at a level responsive to the source voltage. The regulator maintains the negative voltage in response to the source voltage so that the electric field remains essentially constant over a range of values of source voltage.

Regulated voltage supply circuit for inducing tunneling current in floating gate memory devices

The present invention provides a new memory device for storage of boot code for microprocessors which boot to either the top or bottom of a memory map on power-up. The device includes a memory array, a first block, and decoders. The first block is defined as rows of the memory array designated for storage of data. The decoders decode a memory access requested for the data. The memory access request may be in either one of a top-down or bottom-up address protocol. In another embodiment, an integrated circuit memory includes: a memory array, a decoder, a control, and a logic gate. The decoders decode a memory access request to select a row of memory array. The control has an output for outputting either a bottom-up or a top-down address protocol signal. The logic gate outputs a logical 'Exclusive Or' of the control signal and a corresponding bit of the memory access request, whereby a memory request in a bottom-up address protocol is converted to a memory address in a top-down address protocol.

Memory supporting multiple address protocols

Automatic test process with non-volatile result table store

Power on reset circuit

Block decoded wordline driver with positive and negative voltage modes

A recovery circuit for recovering the control gate and the channel well of a floating gate memory cell to a first recovery potential and a second recovery potential respectively after a program or erase process has been performed on the cell is provided. The floating gate memory cell may include the control gate coupled to a first node at a first program/erase potential, a floating gate, the channel well coupled to a second node at a second program/erase potential having a first conductivity type, and drain and source regions within the channel well having a second conductivity type different from the first. The recovery circuit includes control circuitry that provides a recovery control signal indicating when the program or erase process has been completed, and a coupling circuit that connects the control gate to the channel well in response to the recovery control signal. The recovery circuit further includes first and second voltage detectors that generate first and second grounding signals when the control gate and channel well voltages reach a first and second switching voltage respectively. The first and second grounding signals are provided to first and second voltage grounding circuits that bias the control gate and the channel well to the first and second recovery potentials respectively in response to the grounding signals. In one embodiment the first and second recovery potentials are connected to a node at ground potential, and in another embodiment the first conductivity type is p-type. In a further embodiment the floating gate memory cell is a triple well transistor, the channel well of which is within an isolation well on the substrate of an integrated circuit.

Channel FN program/erase recovery scheme

Triple well floating gate memory and operating method with isolated

The negative supply voltage and isolation well bias used by the drivers during sector or chip level erase operations are decoded separately from each other and from the decoding of the inputs of the individual wordline drivers in a compact wordline driver and decoder system. An integrated circuit memory comprising an array of memory cells arranged in a plurality of segments, a set of wordlines is coupled to the memory cells in the array, and wordline driver circuitry using shared isolation well MOS transistors coupled to the set of wordlines is provided. The wordline driver circuitry includes a first supply voltage source, a second supply voltage source, a third supply voltage source for the shared isolation well and a set of wordline drivers. The wordline drivers are coupled to the first, second and third supply voltage sources, and selectively drive wordlines in the set of wordlines with a wordline voltage from either the first supply voltage source or the second supply voltage source in response to address signals which identify the respective drivers. The second supply voltage source includes a set of supply voltage selectors. Each supply voltage selector in the set is coupled with a subset of the set of drivers. The subset of drivers is coupled with a respective segment in the array. The supply voltage selectors select a negative erase supply voltage or an erase inhibit supply voltage during an erase mode in response to address signals identifying the respective segments. The selected negative erase supply voltage or erase inhibit supply voltage is applied to the subsets of the set of drivers which are coupled to the respective segment on a segment by segment basis.

A new flash memory cell structure and operational bias is based on the use of a triple well flash memory cell which allows pre-programming by Fowler Nordheim (F-N) tunneling over blocks of cells at a time. The floating gate memory cell is made in a semiconductor substrate having a first conductivity type, such as p-type. A first well within the substrate by having a second conductivity type different than the first conductivity type is included. A second well within the first well is also included having the first conductivity type. A drain and a source are formed in the second well having the second conductivity type, and spaced away from one another to define a channel area between the drain and the source. A floating gate and control gate structure is included over the channel area. The floating gate memory cell is coupled with circuits that induce F-N tunneling of electrons out of the floating gate into the channel area of the substrate for erasing by applying a positive voltage to the second well, such as a voltage higher than the supply voltage, applying a positive voltage to the first well, which is substantially equal to the positive voltage of the second well, applying a negative voltage to the control gate of the cell, while the substrate is grounded. A block wide pre-program operation involves F-N tunneling of electrons into the floating gate from the channel area, using a negative voltage in the second well.

Fowler-Nordheim (F-N) tunneling for pre-programming in a floating gate

A circuit is provided for supplying a negative erasing voltage onto the wordlines of selected blocks in an array of floating gate memory cells. The circuit includes a voltage circuit, which has a plurality of local outputs, each of which connects to wordlines of an associated block of floating gate memory cells. A block selector circuit is coupled to the local outputs of the voltage circuit and selectively switches each of the local outputs to apply either an erasing voltage or a non-erasing voltage onto the wordlines of the associated block of floating gate memory cells. Negative wordline stress is thus reduced for wordlines of unselected blocks which receive a less negative, non-erasing voltage during block erase operations.

Block-level wordline enablement to reduce negative wordline stress

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Hsin-Pu, Taiwan

Tzeng-Huei Shiau