Altera Corporation

Tze Sin Tan

Chin Hai Ang

Siew Ling Yeoh

Ala-Uddin Ismail

Jayabrata Ghosh Dastidar

Chiew Khiang Kuit

Nen Wei Ng

Chee Lam Ng

The present invention discloses a method of testing an analog-to-digital converter (ADC). The method includes receiving a series of analog signals from a tester site, converting the series of analog signals to a series of digital code words using an ADC, evaluating the ADC based on the series of digital code words using an ADC test setup and generating an output signal identifying whether the ADC has passed the testing.

Method and apparatus for using programmable logic circuitry to test on-chip analog-to-digital converter

An integrated circuit device has first and memory that use first and second normal mode clocks with differing clock domains. A first switching circuit selectively outputs to the first memory the first normal mode clock when the normal mode is selected or the initial test clock as a first test clock when a testing mode is selected, and a second switching circuit selectively outputs to the second memory the second normal mode clock when the normal mode is selected or the test clock as a second test clock when the testing mode is selected. A built-in-self-test switching circuit receives and outputs the first test clock when the first memory is being tested or the second test clock when the second memory is being tested, and a built-in-self-test circuit receives and uses the first test clock for testing the first memory or the second test clock for testing the second memory.

Methods and apparatus for testing multiple clock domain memories

An integrated circuit may have a circuit under test. The integrated circuit may have a clock generation circuit that receives a reference clock from a tester and that generates a corresponding core clock. The integrated circuit may have a built in self test circuit and a clock synthesizer that receives the core clock. The built in self test circuit may provide clock synthesizer control signals that direct the clock synthesizer to produce test clock signals at various test clock frequencies. The test clock at the test clock frequencies may be applied to the circuit under test during circuit testing. The circuit under test may assert a pass signal when the circuit tests are completed successfully. The built in self test circuit may inform the tester of the maximum clock frequency at which the circuit under test successfully passes testing.

Logic circuit testing with reduced overhead

An integrated circuit includes a memory circuit, a read address register coupled to a read address port of the memory circuit, a write address register coupled to a write address port of the memory circuit, and a multiplexer configurable to transmit a read address bit from the write address register to the read address register in response to a read control signal. The read address register loads the read address bit into the memory circuit through the read address port during a test of the memory circuit. The integrated circuit may include a multiplexer configurable to transmit a write address bit from the read address register to the write address register in response to a write control signal. The write address register loads the write address bit into the memory circuit through the write address port during the test of the memory circuit.

Growing community of inventors

Island Glades, Malaysia

Tze Sin Tan