Realtek Semiconductor Inc.

Tze-Min Shen

Chih-Hao Chang

Chin-Yuan Lo

Ting-ying Wu

Hsin Hui Lo

A circuit structure includes a circuit board, microstrips, a stripline, and vias. The circuit board includes conductive levels. A first and second transceiving circuits are disposed on a first conductive level. A first microstrip is disposed on the first conductive level, and configured to couple a first pin of the first transceiving circuit to a second pin of the second transceiving circuit. A second and third microstrips are disposed on the first conductive level, and coupled to a third pin of the first transceiving circuit and a fourth pin of the second transceiving circuit, respectively. The stripline is disposed on a second conductive level. A first and second vias cross the first and second levels, and couple the second and third microstrips to the stripline. The first and third pins are an inner and outer pins of a front line of a BGA of the first transceiving circuit, respectively.

Circuit structure

A layout method is configured to design a layout of a bridging circuit between source circuit and a destination circuit of a circuit system. The layout method includes: categorizing the bridging circuit into sub-regions according to physical structural characteristics; obtaining default sub-region model units corresponding to the sub-regions from a database; setting the default sub-region model units by the parameters to obtain sub-region models; extracting, using an electromagnetic simulation software, electrical models from the sub-region models, respectively; connecting the sub-region models to obtain, using a circuit simulation software an entire electrical model; evaluating whether the entire electrical model meets a specific requirement of the bridging circuit with respect to the circuit system; and when the entire electrical model meets the specific requirement, obtaining a layout rule according to the sub-region models.

Layout method and related non-transitory computer-readable medium

A semiconductor package includes a first chip and a second chip arranged side by side on a carrier substrate. The first chip is provided with a high-speed signal pads along a first side in proximity to the second chip. The second chip includes a redistribution layer, and the redistribution layer is provided with data (DQ) pads along the second side in proximity to the first chip. A plurality of first bonding wires is provided to directly connect the high-speed signal pads to the DQ pads. The redistribution layer of the second chip is provided with first command/address (CA) pads along the third side opposite to the second side, and a plurality of dummy pads corresponding to the first CA pads. The plurality of dummy pads are connected to second CA pads disposed along a fourth side of the second chip via interconnects of the redistribution layer.

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Hsinchu, Taiwan

Tze-Min Shen