Taiwan Semiconductor Manufacturing Comp. Ltd.

Tze-Liang Lee

Chii-Horng Li

Jr-Hung Li

Ming-Hua Yu

Tai-Chun Huang

Kun-Mu Li

Hsueh-Chang Sung

Tsz-Mei Kwok

Ching-Yu Chang

Chien-Hao Chen

Pei-Ren Jeng

Chung-Chi Ko

Yi-Hung Lin

Shih-Chang Chen

Pang-Yen Tsai

Chih-Tang Peng

Hao-Ming Lien

Syun-Ming Jang Jang

Chao-Cheng Chen

Yen-Yu Chen

Chung-Ting Ko

Po-Cheng Shih

Chi-Ming Yang

Li-Ting Wang

Yu-Hung Cheng

Ming-Hui Weng

Yahru Cheng

Tsai-Jung Ho

Kuang-Yuan Hsu

Shing-Chyang Pan

Yen-Ru Lee

Ting-Gang Chen

Chia-Cheng Chou

Chunyao Wang

Mong-Song Liang

Yu-Yun Peng

Su-Jen Sung

Chia-Lin Chen

Chi On Chui

Yung-Cheng Lu

Chun-Feng Nieh

Huan-Just Lin

Shu-Yuan Ku

Tsan-Chun Wang

Yen-Chun Huang

Ling-Yen Yeh

Chan-Lon Yang

Chih-Hao Chen

Yi-Jing Lee

Kuo-Tai Huang

Wan-Yi Kao

Chih-Chien Chi

Chen-Yuan Kao

Yao-Jen Chang

Chi-Chun Chen

Teng-Chun Tsai

Huicheng Chang

Ziwei Fang

Fu-Kai Yang

Li-Te S Lin

Liang-Yin Chen

Su-Hao Liu

Cheng-Tung Lin

De-Fang Chen

Chia-Wei Chang

Kuo-Ju Chen

Yung-Chih Wang

Chien-Hsun Wang

Szu-Ping Tung

Ming-Chang Wen

Chih-Pin Tsao

Yu-Lien Huang

Ryan Chia-Jen Chen

Ming-Ching Chang

Chen-Yu Liu

Yi-Nien Su

Yu-Chang Lin

Chu-Yun Fu

Chyi Shyuan Chern

Zi-Wei Fang

Ming-Jie Huang

Peng-Fu Hsu

Ju-Wang Hsu

Chen-Hua Douglas Yu

Chin-Hsiang Lin

Harry-Hak-Lay Chuang

Chih-Hsin Ko

Bao-Ru Young

Cheng-Hsien Wu

Ming Zhu

Chia-Jen Chen

Shiang-Bau Wang

Joung-Wei Liou

Chia-Ying Lee

Jong-I Mou

Hsien-Hsin Lin

Zhen-Cheng Wu

Yu-Ting Huang

Jong Chen

Jo Fei Wang

A device includes a fin structure, a gate structure, a first source/drain epitaxial structure and, a second source/drain epitaxial structure. The fin structure over a substrate and includes a bottom portion protruding from the substrate and a top portion over the bottom portion. An interface between the bottom portion and the top portion comprises oxygen and has an oxygen concentration lower than about 1.E+19 atoms/cm. The gate structure covers the fin structure. The first source/drain epitaxial structure and the second source/drain epitaxial structure are over the top portion of the fin structure and on opposite sides of the gate structure.

Semiconductor device

A representative method includes forming a photo-sensitive material over a substrate, and forming a cap layer over the photo-sensitive material, and patterning the cap layer. Using the patterned cap layer, a first portion of the photo-sensitive material is selectively exposed to a pre-selected light wavelength to change at least one material property of the first portion of the photo-sensitive material, while preventing a second portion of the photo-sensitive material from being exposed to the pre-selected light wavelength. One, but not both of the following steps is then conducted: removing the first portion of the photo-sensitive material and forming in its place a conductive element at least partially surrounded by the second portion of the photo-sensitive material, or removing the second portion of the photo-sensitive material and forming from the first portion of the photo-sensitive material a conductive element electrically connecting two or more portions of a circuit.

Patterning interconnects and other structures by photo-sensitizing method

A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate and forming a dehydrated film over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form an exposed portion and an unexposed portion of the photoresist layer. The photoresist layer is developed to remove the unexposed portion of the photoresist layer and a first portion of the dehydrated film over the unexposed portion of the photoresist layer. In an embodiment, the method includes etching the substrate by using the exposed portion of the photoresist layer as a mask.

Photoresist layer outgassing prevention

A method for forming a semiconductor device includes providing a base device having a top dielectric layer, forming a sacrificial layer on the top dielectric layer, and patterning the sacrificial layer to form openings. The method also includes depositing first protective dielectric layer and a low-K dielectric layer in the opening and performing planarization to form a first planarized structure including sacrificial regions and low k regions separated by a first protective layer. Next, top portions of the low-k dielectric layer are replaced with a second protective dielectric layer to form a second planarized structure that includes enclosed dielectric structures separated by sacrificial regions. The method further includes replacing the remaining portions of the sacrificial layer with a target metal interconnect material to form a third planarized structure that includes metal interconnect material disposed between enclosed dielectric structures.

Semiconductor device and method for manufacturing the same

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

Methods of forming semiconductor device

An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes providing a first conductive feature in a first dielectric layer; selectively depositing an etch-resistant layer over the first dielectric layer, a sidewall of the etch-resistant layer being coterminous with a sidewall of the first dielectric layer; after selectively depositing the etch-resistant layer, selectively depositing a capping layer over the first conductive feature adjacent the etch-resistant layer, a sidewall of the capping layer being coterminous with a sidewall of the first conductive feature; and forming a second conductive feature over the capping layer, the etch-resistant layer separating the second conductive feature from the first dielectric layer.

Interconnect structures and methods of forming the same

A method of forming a semiconductor device includes forming a photoresist layer over a mask layer, patterning the photoresist layer, and forming an oxide layer on exposed surfaces of the patterned photoresist layer. The mask layer is patterned using the patterned photoresist layer as a mask. A target layer is patterned using the patterned mask layer as a mask.

Method for forming and using mask

A method of forming a semiconductor device includes forming a mask layer over a substrate and forming an opening in the mask layer. A gap-filling material is deposited in the opening. A plasma treatment is performed on the gap-filling material. The height of the gap-filling material is reduced. The mask layer is removed. The substrate is patterned using the gap-filling material as a mask.

Semiconductor device and method

A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.

Semiconductor device, FinFET device and methods of forming the same

Semiconductor devices and methods of manufacture are presented herein in which a etch stop layer is selectively deposited over a conductive contact. A dielectric layer is formed over the etch stop layer and an opening is formed through the dielectric layer and the etch stop layer to expose the conductive contact. Conductive material is then deposited to fill the opening.

Semiconductor devices and methods

A method for manufacturing an integrated circuit includes patterning a plurality of photomask layers over a substrate, partially backfilling the patterned plurality of photomask layers with a first material using atomic layer deposition, completely backfilling the patterned plurality of photomask layers with a second material using atomic layer deposition, removing the plurality of photomask layers to form a masking structure comprising at least one of the first and second materials, and transferring a pattern formed by the masking structure to the substrate and removing the masking structure. The first material includes a silicon dioxide, silicon carbide, or carbon material, and the second material includes a metal oxide or metal nitride material.

A method includes depositing a first dielectric layer over a first conductive feature, depositing a first mask layer over the first dielectric layer, and depositing a second mask layer over the first mask layer. A first opening is patterned in the first mask layer and the second mask layer, the first opening having a first width. A second opening is patterned in a bottom surface of the first opening, the second opening extending into the first dielectric layer, the second opening having a second width. The second width is less than the first width. The first opening is extended into the first dielectric layer and the second opening is extended through the first dielectric layer to expose a top surface of the first conductive feature.

Method for forming interconnect structure

A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, an interlayer dielectric (ILD), and a conductive layer. The ILD is disposed on the substrate. The conductive layer is disposed on the substrate and spaced apart from the ILD by an air gap. The ILD is tapered toward the substrate.

Semiconductor device and method of manufacturing the same

A semiconductor device includes: a substrate; an interconnect structure over the substrate; an etch stop layer over the interconnect structure; and metal-insulator-metal (MIM) capacitors over the etch stop layer. The MIM capacitors includes: a bottom electrode extending along the etch stop layer, where the bottom electrode has a layered structure that includes a first conductive layer, a second conductive layer, and a third conductive layer between the first conductive layer and the second conductive layer, where the first conductive layer and the second conductive layer include a first material, and the third conductive layer includes a second material different from the first material; a first dielectric layer over the bottom electrode; a middle electrode over the first dielectric layer, where the middle electrode has the layered structure; a second dielectric layer over the middle electrode; and a top electrode over the second dielectric layer.

Semiconductor device with integrated metal-insulator-metal capacitors

A method includes forming a dummy gate stack over a semiconductor region, forming gate spacers on opposing sides of the dummy gate stack, forming a source/drain region on a side of the dummy gate stack, forming an inter-layer dielectric over the source/drain region, replacing the dummy gate stack with a replacement gate stack, recessing the replacement gate stack to form a recess between the gate spacers, depositing a liner extending into the recess, depositing a masking layer over the liner and extending into the recess, forming an etching mask covering a portion of the masking layer, and etching the inter-layer dielectric to form a source/drain contact opening. The source/drain region is underlying and exposed to the source/drain contact opening. A source/drain contact plug is formed in the source/drain contact opening. A gate contact plug extends between the gate spacers and electrically connecting to the replacement gate stack.

Dummy hybrid film for self-alignment contact formation

Growing community of inventors

Hsinchu, Taiwan

Tze-Liang Lee