Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Tze Ho Simon Chan

Yang Hong

Yong Wee Francis Poh

Jia Zhen Zheng

Pradeep Yelehanka

Weining Li

Yung-Tao Lin

Francis YongWee Poh

Seng-Keong Victor Lim

Dennis Tan

Shyue Seng Tan

Juan Boon Tan

Elgin Kiok Quek

Wanbing Yi

Danny Pak-Chum Shum

Xinshu Cai

Yi Jiang

Fan Zhang

Soh Yun Siah

Handoko Linewih

Yudi Setiawan

Chor Shu Cheng

Jeffrey Chee

Hao Meng

Tommy Lai

Mousumi Bhat

Sriram Balasubramanian

Hari Balan

Shifeng Zhao

Cheong Sik Yu

A device may include a substrate, and an interlevel dielectric arranged over the substrate. The interlevel dielectric may include a first interlevel dielectric layer in an interconnect level i, the first interlevel dielectric layer having a first interconnect and a second interconnect therein. A nitride block insulator may be arranged over the first interlevel dielectric layer and over the first interconnect and the second interconnect. An opening may be arranged in the nitride block insulator, the opening extending through the nitride block insulator to expose a surface of the first interconnect in the first interlevel dielectric layer. A contact plug may be arranged in the opening of the nitride block insulator. The contact plug at least lines the opening and prevents out-diffusion of conductive material from the first interconnect. A thin film of a passive component may be arranged over the nitride block insulator and over the contact plug.

Thin film based passive devices and methods of forming the same

The present disclosure relates to split gate flash MLC based neuromorphic processing and method of making the same. Embodiments include MLC split-gate flash memory formed over a substrate, the MLC split-gate flash memory embedded with artificial neuromorphic processing to dynamically program and erase each cell of the MLC split-gate flash memory; and sense visual imagery by the artificial neuromorphic processing.

Neuromorphic memories with split gate flash multi-level cell and method of making the same

Semiconductor memory devices and methods for writing data in memory cells are provided. An exemplary method for writing data in a memory cell includes providing the memory cell with a first pull-up transistor, a first power supply line coupled to the first pull-up transistor, a second pull-up transistor, and a second power supply line coupled to the second pull-up transistor. The method further includes applying a primary voltage from the first power supply line to the first pull-up transistor. The method also includes applying a secondary voltage from the second power supply line to the second pull-up transistor, wherein the secondary voltage is higher than the primary voltage. Further, the method includes performing a write operation to save a selected value in the memory cell.

Memory cells and methods for writing data to memory cells

Memory cell, method for operating the memory cell and method for fabricating the memory cell are disclosed. The memory cell includes at least three terminals, a first magnetic tunnel junction (MTJ) structure and a second MTJ structure. The first MTJ is coupled between a first terminal (FT) and a third terminal. A portion of the first MTJ is configured to include a first barrier layer disposed between a first fixed layer and a free layer (FL). A magnetization direction of the FL is used to store data, the magnetization direction being controlled by an electric field. The second MTJ is coupled between the FT and a second terminal, where a portion of the second MTJ is configured to include a second barrier layer disposed between a second fixed layer and the FL, where a tunnel magnetoresistance of the second barrier layer is used to read the data.

Energy efficient three-terminal voltage controlled memory cell

Memory cell, method for operating the memory cell and method of forming the memory cell are disclosed. The memory cell includes a first selector having a first select transistor with a first gate coupled to a first wordline and first and second source/drain (S/D) regions, and a second selector having at least a second select transistor with a second gate coupled to a second wordline and first and second S/D regions. The memory cell includes a first magnetic tunnel junction (MTJ) element coupled between a first bit line and the first S/D region of the first select transistor, and a second MTJ element coupled between a second bit line and the first S/D region of the second select transistor.

Low power memory cell with high sensing margin

A method of fabricating an integrated circuit includes depositing a bottom electrode layer, an MTJ layer, and a top electrode layer over a passivation layer and within a trench of the passivation layer and removing portions of the MTJ layer and the top electrode layer to form an MTJ/top electrode stack over the bottom electrode layer and at least partially within portions of the trench having being reopened by said removing. The method further includes forming a further passivation layer over the MTJ/top electrode stack, forming a further ILD layer of the further passivation layer, and reforming a top electrode layer over the ILD layer and over the MTJ/top electrode stack. Still further, the method includes removing portions of the bottom electrode layer, the further passivation layer, the further ILD layer, and the re-formed top electrode layer to form a bottom electrode/MTJ/top electrode stack.

Methods for fabricatingintegrated circuits with spin torque transfer magnetic randomaccess memory (STT-MRAM) including a passivation layer formed along lateral sidewalls of a magnetic tunnel junction of the STT-MRAM

A multi-bit NVM cell includes a storage unit having resistive elements, such as phase change resistive elements. The NVM cell may be configured as a single port or dual port multi-bit cell. The NVM cell includes primary and secondary cell selectors. The primary selector selects the multi-bit cell while the secondary selector selects a bit within the multi-bit cell. A plurality of storage units can be commonly coupled to a primary selector, facilitating high density applications.

Resistive non-volatile memory

A multi-bit NVM cell includes a storage unit having resistive elements, such as phase change resistive elements. The NVM cell may be configured as a single port or dual port multi-bit cell. The NVM cell includes a cell selector. The cell selector selects the multi-bit cell. When appropriate signals are applied to the NVM cell, the cell selector selects an appropriate resistive element of the storage unit. A plurality of storage units can be commonly coupled to the cell selector, facilitating high density applications.

Stackable non-volatile memory

Disclosed herein are memory cell arrays, semiconductor devices, and methods for fabricating semiconductor devices. In one embodiment, a memory cell array includes first, second, third, and fourth memory cells each having a first transistor and a second transistor. First and second word-lines are coupled with the gates of the first transistors of the first and second memory cells. The second and a third word-line are coupled with the gates of the second transistors of the third and fourth memory cells.

Non-volatile memory cell arrays and methods of fabricating semiconductor devices

An embodiment, relates to a phase changeable memory cell. The phase changeable memory cell is formed with an ultra small contact area formed by filament conductive path. This contact area between a heating electrode and phase changeable material layer is determined by the forming of filament path, which is conductive and much smaller in cross-sectional area than the minimum area that can be achieved by lithography. This leads to high heating efficiency and ultra-low programming current. As the disclosed structure has no requirement on endurance for the formed filament and use phase changeable material rather than filament-forming material to provide high on/off resistance ratio, drawbacks of filament-forming material on low endurance and low sensing margin are avoided in the proposed cell structure. Therefore, by using ReRAM-related filament-forming materials to get sub-litho-dimension conductive path as heating electrode and using high on/off ratio phase changeable material as the storage media, it is possible to reduce the power consumption of phase changeable memory dramatically without the drawbacks of filament-forming materials that are shown in ReRAM.

Nonvolative memory with filament

A phase changeable memory cell is disclosed. In an embodiment of the invention, a phase changeable memory cell is formed with an ultra-small contact area to reduce the programming current. This contact area between heater electrode and phase changeable material is limited by the thickness of thin films rather than lithographic critical dimension in one dimension. As a result, the contact area is much less than the square of lithographic critical dimension for almost every technology node, which is helps in reducing current. To further reduce the current and improve the heating efficiency, heater electrode is horizontally put with its length being tunable so as to minimize the heat loss flowing through the heater to the terminal that connects to the front end switch device. In addition, above and below the heater layer, low-thermal-conductivity material (LTCM) is used to minimize heat dissipation. This results in reduced power consumption of the phase changeable memory cell with improved reliability.

Nonvolative memory

A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming two trenches in the semiconductor substrate to define an active region therebetween. An implanted source region is formed in one of the trenches on one side of the active region. An implanted drain region is formed in the other trench on the other side of the active region. Shallow trench isolations are then formed in the trenches. One or more gates are formed over the active region, and contacts to the implanted source region and the implanted drain region are formed.

Non-volatile memory manufacturing method using STI trench implantation

An integrated circuit and e-beam testing method are disclosed. The integrated circuit includes a test structure with a ground grid, a metal pad having a space therein and positioned within the ground grid, and a metal line connected to the ground grid and positioned in the space. Structures for detecting open circuits and short circuits are described.

Planar voltage contrast test structure

An integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.

Growing community of inventors

Singapore, Singapore

Tze Ho Simon Chan