Altera Corporation

Tze Haw Liew

Joo Ming Too

Kok Yoong Foo

Circuits, methods, and apparatus that provide the improvement or recovery of a duty cycle of a clock signal. One embodiment of the present invention receives a clock signal that may have a degraded duty cycle. The frequency of the clock signal is divided by two. The frequency-divided signal is delayed in order to generate two signals that are phase shifted from one another by 90 degrees. These signals are then exclusive-ORed together to generate a recovered clock. A control loop is provided to adjust the phase shift between the signals to be approximately 90 degrees.

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Sarawak, Malaysia

Tze Haw Liew