Applied Materials, Inc.

Tza-Jing Gung

Xianmin Tang

Keith A Miller

Rongjun Wang

John C Forster

Anantha K Subramani

Hong Sheng Yang

Deenesh Padhi

Srinivas Gandikota

Kirankumar Neelasandra Savandaiah

Praburam Gopalraja

Andrew Nguyen

Philip Allan Kraus

Muhammad M Rasheed

Xinhai Han

Adolph Miller Allen

Joseph F AuBuchon

Jianxin Lei

Ilya Lavitsky

Zhendong Liu

Kartik Ramaswamy

Yang Yang

Yu Lei

Yong Cao

Mukund Srinivasan

Praket Prakash Jha

Steven Lane

Edward P Hammond

Vincent E Burkhart

Tae Hong Ha

Travis Koh

Vijay D Parkhe

Peijun Ding

Shahid Rauf

Arvind Sundarrajan

Michael D Willwerth

Samer Banna

Xinyu Fu

Hari K Ponnekanti

Ankur Agarwal

Jingmei Liang

Chunlei Zhang

Joung Joo Lee

Zhenbin Ge

Lei Zhou

Benjamin Schwarz

Jothilingam Ramalingam

Haitao Wang

Zhiqiang Guo

Masaki Ogata

Marc O Schweitzer

Shane Lavan

Jinrui Guo

Xuesong Lu

Wenting Hou

Nobuyuki Sasaki

Yufei Hu

Mei Yin Chang

Vivek G Gupta

Juan Carlos Rocha-Alvarez

Hua Chung

Pramit Manna

Amit Kumar Bansal

Michael Santiago Cox

Lara Hawrylchak

S M Reza Sadjadi

Valentin Nikolov Todorow

Renu Whig

Dan A Marohl

Abdul Aziz Khaja

Alan A Ritchie

Timothy Joseph Franklin

Eswaranand Venkatasubramanian

Ted Tie Guo

Ramprakash Sankarakrishnan

Yogananda Sarode Vishwanath

Prashanth Kothnur

Zhong Qiang Hua

Vladimir Knyazik

Jonghoon Baek

Jick M Yu

Kyle Tantiwong

Hang Yu

Michael Wenyoung Tsiang

Thanh X Nguyen

Jie Zhou

Fernando Silveira

Reza Sadjadi

Donny Young

Juan Carlos Rocha

Daemian Raj Benjamin Raj

Xue Chang

Shailendra Srivastava

Samuel E Gottheim

Hanbing Wu

Milind Gadre

Kishor Kumar Kalathiparambil

Yongjing Lin

Nikhil Sudhindrarao Jorapur

Adam J Fischbach

Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHFgases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH—NFplasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.

Directional selective junction clean with field polymer protections

Embodiments of process kits for use in a process chamber are provided herein. In some embodiments, a process kit for use in a process chamber includes: a chamber liner having a tubular body with an upper portion and a lower portion; a confinement plate coupled to the lower portion of the chamber liner and extending radially inward from the chamber liner, wherein the confinement plate includes a plurality of slots; a shield ring disposed within the chamber liner and movable between the upper portion of the chamber liner and the lower portion of the chamber liner; and a plurality of ground straps coupled to the shield ring at a first end of each ground strap of the plurality of ground straps and to the confinement plate at a second end of each ground strap to maintain electrical connection between the shield ring and the chamber liner when the shield ring moves.

Metal oxide preclean chamber with improved selectivity and flow conductance

A physical vapor deposition processing chamber is described. The processing chamber includes a target backing plate in a top portion of the processing chamber, a substrate support in a bottom portion of the processing chamber, a deposition ring positioned at an outer periphery of the substrate support and a shield. The substrate support has a support surface spaced a distance from the target backing plate to form a process cavity. The shield forms an outer bound of the process cavity. In-chamber cleaning methods are also described. In an embodiment, the method includes closing a bottom gas flow path of a processing chamber to a process cavity, flowing an inert gas from the bottom gas flow path, flowing a reactant into the process cavity through an opening in the shield, and evacuating the reaction gas from the process cavity.

Cleaning of SIN with CCP plasma or RPS clean

Methods and systems are described for generating assessment maps. A method includes receiving a first vector map comprising a first set of vectors each indicating a distortion of a particular location on a substrate and generating a second vector map indicating a change in direction of a magnitude of the distortion of the particular location on the substrate. The method further includes generating a third vector map comprising vectors reflecting reduced noise in distortions across the plurality of locations on the substrate and generating a fourth vector map projecting a direction component of each vector component in the third set of vectors to a radial direction. The method further includes generating a fifth vector map by grouping the vectors of the fourth set of vectors and determining a magnitude associated with each group of vectors.

Analyzing in-plane distortion

Cleaning of sin with CCP plasma or RPS clean

Methods and apparatus for processing a substrate are provided herein. For example, a processing chamber for processing a substrate comprises a sputtering target, a chamber wall at least partially defining an inner volume within the processing chamber and connected to ground, a power source comprising an RF power source, a process kit surrounding the sputtering target and a substrate support, an auto capacitor tuner (ACT) connected to ground and the sputtering target, and a controller configured to energize the cleaning gas disposed in the inner volume of the processing chamber to create the plasma and tune the sputtering target using the ACT to maintain a predetermined potential difference between the plasma in the inner volume and the process kit during the etch process to remove sputtering material from the process kit, wherein the predetermined potential difference is based on a resonant point of the ACT.

Methods and apparatus for processing a substrate

Methods, systems, and non-transitory computer readable medium are described for generating assessment maps for corrective action. A method includes receiving a first vector map including a first set of vectors each indicating a distortion of a particular location of a plurality of locations on a substrate. The method further includes generating a second vector map including a second set of vectors by rotating a position of each vector in the first set of vectors. The method further includes generating a third vector map including a third set of vectors based on vectors in the second set of vectors and corresponding vectors in the first set of vectors. The method further includes generating a fourth vector map by subtracting each vector of the third set of vectors from a corresponding vector in the first set of vectors. The fourth vector map indicates a planar component of the first vector map.

Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

Silicon-containing layer for bit line resistance reduction

Embodiments described herein relate to magnetic and electromagnetic systems and a method for controlling the density profile of plasma generated in a process volume of a PECVD chamber to affect deposition profile of a film. In one embodiment, a plurality of retaining brackets is disposed in a rotational magnetic housing of the magnetic housing systems. Each retaining bracket of the plurality of retaining brackets is disposed in the rotational magnetic housing with a distance d between each retaining bracket. The plurality of retaining brackets has a plurality of magnets removably disposed therein. The plurality of magnets is configured to travel in a circular path when the rotational magnetic housing is rotated around the round central opening.

Magnetic housing systems

Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHFgases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH&#x2014;NFplasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are&#x2014;etched only minimally or not at all.

An apparatus and a method for depositing a film layer that may have minimum contribution to overlay error after a sequence of deposition and lithographic exposure processes are provided. In one example, a method includes positioning a substrate on a substrate support in a process chamber, and flowing a deposition gas mixture comprising a silicon containing gas and a reacting gas to the process chamber through a showerhead having a convex surface facing the substrate support or a concave surface facing the substrate support in accordance with a stress profile of the substrate. A plasma is formed in the presence of the deposition gas mixture in the process chamber by applying an RF power to multiple coupling points of the showerhead that are symmetrically arranged about a center point of the showerhead. A deposition process is then performed on the substrate.

Film stack overlay improvement

Embodiments of process kit shields and process chambers incorporating same are provided herein. In some embodiments a process kit configured for use in a process chamber for processing a substrate includes a shield having a cylindrical body having an upper portion and a lower portion; an adapter section configured to be supported on walls of the process chamber and having a resting surface to support the shield; and a heater coupled to the adapter section and configured to be electrically coupled to at least one power source of the processes chamber to heat the shield.

Physical vapor deposition (PVD) chamber with in situ chamber cleaning capability

Embodiments described herein relate to manufacturing layer stacks of oxide/nitride (ON) layers with minimized in-plane distortion (IPD) and lithographic overlay errors. A method of forming a layer stack ON layers includes flowing a first silicon-containing gas, an oxygen-containing gas, and a first dilution gas. A RF power is symmetrically applied to form a first material layer of SiO. A second silicon-containing gas, a nitrogen-containing gas, and a second dilution gas are flowed. A second RF power is symmetrically applied to form a second material layer of SiN. The flowing the first silicon-containing gas, the oxygen-containing gas, and the first dilution gas, the symmetrically applying the first RF power, the flowing the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas, and the symmetrically applying the second RF power is repeated until a desired number of first material layers and second material layers make up a layer stack.

On stack overlay improvement for 3D NAND

Embodiments disclosed herein relate to cluster tools for forming and filling trenches in a substrate with a flowable dielectric material. In one or more embodiments, a cluster tool for processing a substrate contains a load lock chamber, a first vacuum transfer chamber coupled to the load lock chamber, a second vacuum transfer chamber, a cooling station disposed between the first vacuum transfer chamber and the second vacuum transfer chamber, a factory interface coupled to the load lock chamber, a plurality of first processing chambers coupled to the first vacuum transfer chamber, wherein each of the first processing chambers is a deposition chamber capable of performing a flowable layer deposition, and a plurality of second processing chambers coupled to the second vacuum transfer chamber, wherein each of the second processing chambers is a plasma chamber capable of performing a plasma curing process.

Cyclic flowable deposition and high-density plasma treatment processes for high quality gap fill solutions

Growing community of inventors

San Jose, CA, United States of America

Tza-Jing Gung