Sandisk Technologies Inc.

Sandisk 3d LLC

Tz-Yi Liu

Tianhong Yan

Gopinath Balakrishnan

Eran Sharon

Idan Alrod

Ariel Navon

Yuheng Zhang

Yan Li

Luca Giovanni Fasoli

Yingchang Chen

Jeffrey Koon Yee Lee

Ali K Al-Shamma

Henry Zhang

Roy E Scheuerlein

Alexander Bazarsky

Chang Hua Siau

Omer Fainzilber

Marco Cazzaniga

Jingwen Ouyang

Yibo Yin

Yadhu Vamshi Vancha

Yehuda Hahn

Menahem Lasser

Christopher John Petti

Ran Zamir

George Samachisa

Toru Miwa

Xiying Costa

Stella Achtenberg

Yoocharn Jeon

Ishai Ilani

Po-Shen Lai

Perumal Ratnam

Alon Eyal

Noam Presman

James B Hart

Chandrasekhar R Gorla

Hiroyuki Mizukoshi

Vijay Chinchole

Yibo Nian

Jeffrey Lee

Tim Chen

Jayesh Pakhale

Spyridon Georgakis

Gordon Yee

Magnetic random-access memory (MRAM) circuits are provided herein. In one example implementation, an MRAM circuit includes control circuitry coupled to a magnetic tunnel junction (MTJ) element in series with a selector element. This control circuitry is configured to adjust current through the selector element when the selector element is in a conductive state. The circuit also includes a compensation circuitry configured to compensate for a offset voltage across the selector element in the conductive state based on adjustments to the current through the selector element. An output circuit is also configured to report a magnetization state of the MTJ element.

Magnetic random-access memory with selector voltage compensation

A circuit or associated system or apparatus includes a first transistor, a second transistor, a first switch, a second switch, a first current source, and a third switch. The first transistor is configured to sample a first current of a control line. The second transistor is configured to apply a second current to the control line. The second transistor is also configured to match the second current to the first current. The first switch is connected in series between a control terminal of the first transistor and a control terminal of the second transistor. The second switch is connected in series between the second transistor and the control line. The third switch is connected in series between the first current source and the control line.

Fast voltage compensation without feedback

One or more control lines other than those used to activate a non-volatile memory cell may be used to sense a data value of the cell. For example, an apparatus may include a selection circuit that selects, based on an address corresponding to a non-volatile memory cell included an array of non-volatile memory cells, a word line coupled to the non-volatile memory cells to activate the non-volatile memory cell. An amplifier circuit may sense a data value stored in the non-volatile memory cell based on a sense signal having a voltage level based on voltage levels of one or more other word lines of the array of non-volatile memory cells. In another example, a data value of a non-volatile memory cell coupled to a word line may be sensed based on the voltage levels of one or more dummy sense lines within the array.

Sensing memory cells using array control lines

Apparatuses, systems, methods, and computer program products are disclosed for a multicore on-die memory controller. An integrated circuit device includes an array of non-volatile memory cells and a microcontroller unit. A microcontroller unit includes a plurality of processing units. Different processing units perform different categories of tasks in parallel for an array of non-volatile memory cells.

Multicore on-die memory microcontroller

A sequencer circuit is configured to generate control signals for on-die memory control circuitry. The control signals may include memory operation pulses for implementing operations on selected non-volatile memory cells embodied within the same die as the sequencer (and other on-die memory control circuitry). The timing, configuration, and/or duration of the memory control signals are defined in configuration data, which can be modified after the design and/or fabrication of the die and/or on-die memory circuitry. As such, the timing, configuration, and/or duration of the memory control signals generated by the sequencer may be manipulated after the design and/or fabrication of the die, sequencer, and other on-die memory control circuitry.

Systems and methods for on-die control of memory command, timing, and/or control signals

Apparatuses, systems, and methods are disclosed for controlling a data path for non-volatile memory. An apparatus includes one or more memory die. A memory die includes a memory core. A memory core includes an array of non-volatile memory cells and an internal data pipeline. A memory die includes a buffer that stores data associated with storage operations for a memory core. A memory die includes an internal controller that communicates with a memory core to initiate storage operations. An internal controller may delay initiating a storage operation in response to determining that an internal data pipeline and a buffer are both full.

Data path control for non-volatile memory

A calibration circuit coupled to a sense amplifier circuit may be configured to determine a response time of the sense amplifier circuit relative to a pulse sequence. Based on the determined response time, the calibration circuit may be configured to set a level of a biasing current to a desired level in order to control the response time of the sense amplifier circuit.

Sense amplifier calibration

A method includes, in a data storage device including a resistive memory, receiving, from an external device, an erase command to erase a portion of the resistive memory. The method further includes storing shaped data at the portion of the resistive memory responsive to the erase command. Shaped data is configured to control an amount of leakage current during a read and/or write operation at one or more storage elements that are adjacent to at least one storage element of the portion of the resistive memory.

Shaped data associated with an erase operation

Technology is described for keeping current (e.g., peak power supply current or ICC) in a non-volatile memory system within a target while maintaining high throughput. Programming conditions are adaptively changed at the sub-codeword level in order to keep power supply current of the memory system within a target. In one embodiment, a chunk of data that corresponds to a sub-codeword is written while consuming lower than normal programming current in order to keep power supply current within a target. The relatively low programming current may increase the expected raw BER. However, other portions of the codeword can be written with a higher than normal programming current, which results in a lower expected bit raw error rate for the memory cells that store that portion.

Peak current management in non-volatile storage

Apparatuses, systems, methods, and computer program products are disclosed for redundancy mapping. A controller is configured to determine that one or more defects affect a subset of a first group of cells and a subset of a second group of cells of a non-volatile memory medium. A non-volatile memory medium may include a plurality of groups of cells, and redundant groups of cells may be available for replacing defective groups of cells. A controller is configured to store a mapping between affected subsets of first and second groups of cells and a redundant group of cells for a non-volatile memory medium. A controller is configured to read data for a first group and/or second group of cells by referencing a mapping and using a redundant group of cells.

Dynamic-shifting redundancy mapping for non-volatile data storage

A data storage device includes a memory die. The memory die includes a resistive random access memory (ReRAM) having a first portion and a second portion that is adjacent to the first portion. A method includes determining whether to access the second portion of the ReRAM in response to initiating a first operation targeting the first portion of the ReRAM. The method further includes initiating a second operation that senses information stored at the second portion to generate sensed information in response to determining to access the second portion. The method further includes initiating a third operation to rewrite the information at the ReRAM in response to detecting an indication of a disturb condition based on the sensed information.

Disturb condition detection for a resistive random access memory

A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.

Program cycle skip

A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times.

Apparatus and methods for sensing hard bit and soft bits

A data storage device includes a resistive random access memory (ReRAM). The data storage device includes read circuitry coupled to a storage element of the ReRAM. The read circuitry is configured to read a data value from the storage element, during a read operation, based on a read current sensed during a first phase of the reading operation and a leakage current sensed during a second phase of the reading operation. The data storage device also includes a controller coupled to the read circuitry. The controller is configured to provide an input value to an error correction coding (ECC) decoder, where the input value includes a hard bit value and a soft bit value. The hard bit value corresponds to the data value, and the soft bit value is at least partially based on the leakage current.

Reading resistive random access memory based on leakage current

A multi-stage charge pump selects the number of active stages dynamically. In the exemplary embodiment, this is done by having a multi-stage master charge pump section in which the number of active stages is settable and a slave charge pump section that is of the same design as the master section. The master section is used to drive the external load, while the slave section drives an adjustable internal load. The adjustable internal load is set by control logic by comparing the operation of the two sections. The control logic then operates the slave section with a different number of active stages than the master stage in order to determine whether the master stage is using the optimal number of active stages. The control logic can then change the number of active stages accordingly.

Charge pump system that dynamically selects number of active stages

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Palo Alto, CA, United States of America

Tz-Yi Liu