Taiwan Semiconductor Manufacturing Comp. Ltd.

Tz-Jun Kuo

Ming-Han Lee

Shin-Yi Yang

Hsiang-Huan Lee

Shau-Lin Shue

Chien-Hsin Ho

Ching-Fu Yeh

Ming Han Lee

Meng-Pei Lu

Chi-Liang Kuo

Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.

Interconnect structure without barrier layer on bottom surface of via

A device includes a first conductive feature disposed over a substrate; a second conductive feature disposed directly on and in physical contact with the first conductive feature; a dielectric layer surrounding sidewalls of the second conductive feature; and a first barrier layer interposed between the second conductive feature and the dielectric layer and in physical contact with both the second conductive feature and the dielectric layer. The first barrier layer and the dielectric layer comprise at least two common elements.

Method of forming metal interconnection

Vias and methods of making the same. The vias including a middle portion located in a via opening in an interconnect-level dielectric layer, a top portion including a top head that extends above the via opening and extends laterally beyond upper edges of the via opening and a bottom portion including a bottom head that extends below the via opening and extends laterally beyond lower edges of the via opening. The via may be formed from a refractory material.

Via structure and methods for forming the same

A method of fabricating a semiconductor device is disclosed. The method includes forming a first conductive feature over a substrate, forming a dielectric layer over the first conductive feature, forming a via trench in the dielectric layer, forming a first barrier layer in the via trench. Therefore the first barrier has a first portion disposed over the dielectric layer and a second portion disposed over the first conductive feature, applying a thermal treatment to convert the first portion of the barrier layer to a second barrier layer and exposing the first conductive feature in the via trench while a portion of the second barrier layer is disposed over the dielectric layer.

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned dielectric layer with a plurality of openings is formed on the substrate. A barrier layer is deposited in the openings by a first tool and a sacrificing protection layer is deposited on the barrier layer by the first tool. The sacrificing layer is removed and a metal layer is deposited on the barrier layer by a second tool.

Method of forming an interconnection

Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.

Method for via plating with seed layer

A method of fabricating a semiconductor device is disclosed. The method includes forming a first conductive feature over a substrate, forming a dielectric layer over the first conductive feature, forming a trench in the dielectric layer, forming a first barrier layer in the trench, applying a thermal treatment to convert a first portion of the barrier layer to a second barrier layer, exposing the first conductive feature in the trench while a portion of the second barrier layer is disposed over the dielectric layer and forming a second conductive feature in the trench.

The present disclosure relates to a method of forming a back-end-of-the-line metal interconnect layer. The method is performed by depositing one or more self-assembled monolayers on a semiconductor substrate to define a metal interconnect layer area. A metal interconnect layer having a plurality of metal structures is formed on the semiconductor substrate within the metal interconnect layer area. An inter-level dielectric layer is then formed onto the surface of the semiconductor substrate in areas between the plurality of metal structures.

Growing community of inventors

Hsinchu County, Taiwan

Tz-Jun Kuo