United Microelectronics Corp.

Tz-Guei Jung

Joe Ko

Chia-Hsin Hou

Jacob Chen

Keh-Ching Huang

Tung-Po Chen

Wen-Jeng Lin

Jyh-Kuang Lin

Tzu-Min Peng

A method for manufacturing a capacitor. A semiconductor substrate is divided into a peripheral circuit region and a memory cell region. An isolation structure is formed in the memory cell region. A gate oxide layer is formed over the substrate outside the isolation structure. A polysilicon layer is formed over the gate oxide layer and the isolation structure. The polysilicon layer and the gate oxide layer are patterned to form a bottom electrode above the isolation structure. In the meantime a polysilicon gate electrode is also formed above the peripheral circuit region. Spacers are formed on the sidewalls of the polysilicon gate electrode and the bottom electrode. A metal silicide layer is formed over the bottom electrode and the polysilicon gate electrode. A dielectric layer is formed over the metal silicide layer above the bottom electrode. A metallic layer is formed over the dielectric layer to form a capacitor.

Method for manufacturing capacitor

A method for manufacturing a capacitor is provided in the present invention. The bottom electrode of the capacitor is a polysilicon layer, and the top electrode of the capacitor is a silicide layer. Since depletion regions cannot be generated in the metal layer or the suicide layer, and the resistivity of the metal layer or the silicide layer is smaller than a conventional polysilicon layer, so that operating speed and frequency of the capacitor are both increased.

A method of manufacturing wells comprises the step of providing a p-type substrate and then sequentially forming a p-well and n-well with low dosage in the p-type substrate. Thereafter, energy is used to dope n-type ions into the p-well. The triple well formed in the present invention has low dosage ions, hence the DRAM formed on the triple well in subsequent process can have a faster refresh time.

Method of fabricating well

A method for fabricating a capacitor is applicable to a fabrication process for a mixed circuit. The method involves forming a first dielectric layer, a stop layer, and a second dielectric layer on a substrate having a conductive region. A first opening is then formed in the second dielectric layer, followed by forming a second opening in the stop layer and the first dielectric layer, so that the first opening and the second opening form a dual damascene opening for exposing the conductive region. The dual damascene opening is filled with a first conductive layer, so as to form a via plug and a lower electrode of the capacitor for connecting to the conductive region. A third dielectric layer, which is located between the lower electrode and a subsequent formed upper electrode, is then formed over the substrate, so that the lower electrode and a part of the second dielectric layer adjacent to the lower electrode are completely covered by the third dielectric layer. A patterned second conductive layer is formed on a part of the third dielectric layer, whereby an upper electrode for completely covering the lower electrode is formed.

Method of fabricating a mixed circuit capacitor

The invention provides a manufacturing method of forming a bottom plate for a capacitor on a substrate, wherein the substrate comprises a MOS transistor having a gate and a pair of source/drain regions. A crown-liked conductive plate is formed over an insulation oxide layer and a contact plug. The crown-liked conductive plate penetrates the insulation layer and the stop layer, wherein the bottom of the crown-like conductive plate is electrically connected to the contact plug. The crown-like conductive plate, served as the bottom plate for a DRAM capacitor, is composed of tungsten silicide or a combination of a tungsten nitride layer and a tungsten layer.

Manufacturing method of a bottom plate

A planarization method used in fabricating an embedded dynamic random access memory (DRAM). After a number of metal-oxide semiconductor (MOS) transistors and a number of capacitors are formed on a semiconductor substrate, a first inter-layer di-electric (ILD) layer is formed over the substrate. The embedded DRAM is divided into a memory region and a logic region. Next, planarization is performed. A dummy metal layer is formed and coupled to an interchangeable source/drain region of the MOS transistor in the logic region. Then a second ILD layer is formed over the logic region to compensate difference in height between the logic region and the memory region. Then, a via hole/plug is formed in the logic region to extend the first metal layer. A second metal layer with required contact window/plugs is formed over the substrate.

Growing community of inventors

Hsinchu, Taiwan

Tz-Guei Jung