Advanced Micro Devices Corporation

Spansion Llc.

Tyagamohan Gottipati

Minh Van Ngo

Ning Cheng

Angela Tai Hui

Dawn M Hopper

Tazrien Kamal

Robert A Huertas

Jeff P Erhardt

Clarence B Ferguson

Mark T Ramsbey

Jeffrey Allan Shields

Arvind Halliyal

Jaeyong Park

John Caffall

Kuo-Tung Chang

Cyrus E Tabery

Wenmei Li

Jean Yee-Mei Yang

Atul Gupta

Pei-Yuan Gao

Kelwin King Wai Ko

Jeyong Park

A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell including a charge trapping dielectric charge storage layer in a semiconductor device; and during processing steps subsequent to formation of the charge trapping dielectric charge storage layer, protecting the charge trapping dielectric flash memory cell from exposure to a level of UV radiation sufficient to deposit a non-erasable charge in the charge trapping dielectric flash memory cell. In one embodiment, the step of protecting is carried out by selecting processes in BEOL fabrication which do not include use, generation or exposure of the semiconductor device to a level of UV radiation sufficient to deposit the non-erasable charge.

Protection of charge trapping dielectric flash memory devices from UV-induced charging in BEOL processing

Semiconductor devices with improved data retention are formed by depositing an undoped oxide liner on spaced apart transistors followed by in situ deposition of a BPSG layer. Embodiments include depositing an undoped silicon oxide liner derived from TEOS, as at a thickness of 400 &#x212b; to 600 &#x212b;, on transistors of a non-volatile semiconductor device, as by sub-atmospheric chemical vapor deposition, followed by depositing the BPSG layer in the same deposition chamber.

Undoped oxide liner/BPSG for improved data retention

A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material. In one embodiment, the device includes a substantially UV-opaque sub-layer of a contact cap layer or a substantially UV-opaque contact cap layer.

UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processing

Device leakage due to spacer undercutting is remedied by depositing a B-doped HDP or a BP-doped HDP oxide gap filling layer capable of flowing into undercut regions. Embodiments include depositing a B or BP-doped HDP oxide film containing 4 to 6 wt. % B over closely spaced apart non-volatile transistors and heating during and subsequent to deposition to complete flowing of the B- or BP-HDP oxide into and filling the undercut regions on the sidewall spacers and to densify the B- or BP-HDP oxide.

Reflowable-doped HDP film

A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material. A SONOS flash memory device, including a SONOS flash memory cell; and at least one UV-protective layer, in which the UV-protective layer comprises a substantially UV-opaque material, is provided. In one embodiment, the device includes a substantially UV-opaque contact cap layer.

UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL

Device leakage due to spacer undercutting is remedied by depositing a BPSG, SA-CVD oxide liner and flowing it into the undercut regions, followed by gap filling with a P-doped HDP oxide layer. Embodiments include depositing a BPSG, SA-CVD oxide liner containing 4 to 6 wt.% boron, at a thickness of 1,000 &angst; to 1,800 &angst;, over closely spaced apart non-volatile transistors and heating during or subsequent to deposition to flow the BPSG, SA-CVD oxide liner into the undercut regions of the sidewall spacers of the gate stacks. Gap filling is then completed by depositing the layer of P-doped HDP at a thickness of 6,000 &angst; to 10,000 &angst;.

BPSG, SA-CVD liner/P-HDP gap fill

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Sunnyvale, CA, United States of America

Tyagamohan Gottipati