Northrop Grumman Systems Corporation

Ty Richard McNutt

John V Veliadis

Eric Jonathan Stewart

Li-shu Chen

Stephen Van Campen

John Vincent Reichl

Megan Jean McCoy

Robert Miles Young

Narsingh Bahadur Singh

Rowland C Clarke

Andre E Berghmans

Brian Paul Wagner

David A Kahler

David J Knuteson

Kenneth J Petrosky

Thomas J Knight

Marc Eisenzweig Sherwin

Ranbir Singh

Sean R McLaughlin

Jerry W Hedrick

George M Bates

David Everett Bulgher

Harold C Heame, Iii

The disclosure relates to a high purity 2H-SiC composition and methods for making same. The embodiments represented herein apply to both thin film and bulk growth of 2H-SiC. According to one embodiment, the disclosure relates to doping an underlying substrate or support layer with one or more surfactants to nucleate and grow high purity 2H-SiC. In another embodiment, the disclosure relates to a method for preparing 2H-SiC compositions by nucleating 2H-SiC on another SiC polytype using one or more surfactants. The surfactants can include AlN, Te, Sb and similar compositions. These nucleate SiC into disc form which changes to hexagonal 2H-SiC material.

Method and apparatus for growing high purity 2H-silicon carbide

Systems and methods for maximizing the breakdown voltage of a semiconductor device are described. In a multiple floating guard ring design, the spacing between two consecutive sets of floating guard rings may increase with their distance from the main junction while maintaining depletion region overlap, thereby alleviating crowding and optimally spreading the electric field leading to a breakdown voltage that is close to the intrinsic material limit. In another exemplary embodiment, fabrication of floating guard rings simultaneously with the formation of another semiconductor feature allows precise positioning of the first floating guard ring with respect to the edge of a main junction, as well as precise control of floating guard ring widths and spacings. In yet another exemplary embodiment, design of the vertical separation between doped regions of a semiconductor device adjusts the device's gate-to-source breakdown voltage without affecting the device's pinch-off voltage.

Systems and methods for maximizing breakdown voltage in semiconductor devices

In an embodiment, a integrated semiconductor device includes a first Vertical Junction Field Effect Transistor (VJFET) having a source, and a gate disposed on each side of the first VJFET source, and a second VJFET transistor having a source, and a gate disposed on each side of the second VJFET source. At least one gate of the first VJFET is separated from at least one gate of the second VJFET by a channel. The integrated semiconductor device also includes a Junction Barrier Schottky (JBS) diode positioned between the first and second VJFETs. The JBS diode comprises a metal contact that forms a rectifying contact to the channel and a non-rectifying contact to at least one gate of the first and second VJFETs, and the metal contact is an anode of the JBS diode. A first electrical connection ties the gates of the first VJFET, the gates of the second VJFET, and the anode of the JBS diode to a common gate electrode and a second electrical connection ties the source of the first VJFET and the source of the second VJFET to a common source electrode.

Power switching transistors

An exemplary edge termination structure maintains the breakdown voltage of the semiconductor device after it has been sawed off the wafer and packaged by creating an electric field stop layer at a periphery of the semiconductor device. The electric field stop layer has a dopant concentration higher than that of the layer in which an edge termination is implemented, such as a drift layer or a channel layer. The electric field stop layer may be created by selectively masking the peripheries of the device during the device processing, i.e., mesa etch, to protect and preserve the highly doped material at the peripheries of the device.

Semiconductor structure with an electric field stop layer for improved edge termination capability

A gate drive circuit for a wide bandgap semiconductor junction gated transistor includes a gate current limit resistor. The gate current limit resistor is coupled to a gate input of the wide bandgap semiconductor junction gated transistor when in use and limits a gate current provided to the gate input of the junction gated transistor. An AC-coupled charging capacitor is also included in the gate drive circuit. The AC-coupled charging capacitor is coupled to the gate input of the wide bandgap semiconductor junction gated transistor when in use and is positioned parallel to the gate current limit resistor. A diode is coupled to the gate current limit resistor and the AC-coupled charging capacitor on one end and an output of a gate drive chip on the other end When in use, the diode lowers a gate voltage output from the gate drive chip applied to the gate input of the wide bandgap semiconductor junction gated transistor through the gate current limit resistor. The gate drive circuitry provides a small, efficient, and cost effective control circuitry for a wide bandgap semiconductor junction gated transistor.

Gate drive for wide bandgap semiconductor device

A normally-off cascode power switch circuit is disclosed fabricated in wide bandgap semiconductor material such as silicon carbide or gallium nitride and which is capable of conducting current in the forward and reverse direction under the influence of a positive gate bias. The switch includes cascoded junction field effect transistors (JFETs) that enable increased gain, and hence blocking voltage, while minimizing specific on-resistance.

Cascode power switch topologies

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Columbia, MD, United States of America

Ty Richard McNutt