Dell Products Inc.

Dell USA L.p.

Tuyet-Huong Thi Nguyen

Mukund Purshottam Khatri

Vijay Bharat Nijhawan

David Keith Chalfant

Robert Wayne Hormuth

Vadhiraj Sankaranarayanan

Amit Shah

Jose M Grande

Austin Patrick Bolen

Andrew Butcher

Robert G Bassman

Wai-Ming Richard Chan

Wei Liu

Albert John Bolian

Mark Lawrence Farley

René Franco

James R Pledge

Prakash Chauhan

A Peripheral Component Interconnect express (PCIe) Downstream Port Containment (DPC) System Management Interrupt (SMI) storm prevention system includes a Basic Input/Output System (BIOS) subsystem coupled to a first PCIe device. In response to an error being experienced in the first PCIe device and causing the first PCIe device to perform DPC operations, the BIOS subsystem receives a plurality of SMIs that are each configured to begin a System Management Mode (SMM). The BIOS subsystem tracks a number of the plurality of SMIs in a BIOS database and determines when the number of the plurality of SMIs has reached a DPC SMI storm threshold. In response to the number of the plurality of SMIs reaching the DPC SMI storm threshold, the BIOS subsystem prevents use of a link to the first PCIe device and prevents an operating system from performing recovery operations to recover the first PCIe device from the error.

PCIE DPC SMI storm prevention system

A method, an information handling system (IHS) and a memory mirroring system for operating a mirrored memory. The method includes detecting, via a memory controller, at least one uncorrectable data error (UCDE) in a first memory device. In response to detecting the at least one UCDE, a UCDE event counter is retrieved that tracks the number of UCDE events that have occurred and a UCDE event threshold is retrieved corresponding to a maximum number of allowed UCDE events. The method further includes determining if the UCDE event counter is greater than the UCDE event threshold and in response to determining that the UCDE event counter is not greater than the UCDE event threshold, continuing writing of data to the first memory device via a first memory channel and continuing writing of the data to a second memory device via a second memory channel to create a mirror of the data.

Memory mirroring in an information handling system

Systems and methods for preventing system crashes due to memory link failure in memory mirroring mode in an information handling system (IHS). The IHS may include a first memory device, a second memory device, and an integrated memory controller (IMC). The IMC may issue write transactions to both the first and second memory devices and issue read transactions to the first memory device when the IMC is in memory mirroring mode. The IMC may transmit a system management interrupt (SMI) with an IMC error to a basic input/output system (BIOS) when a persistent uncorrected IMC error is detected within the first memory device. The BIOS may perform a memory mirror failover process that may cause the IMC to issue the write transactions and the read transactions to the second memory device when the IMC error is a fatal memory link error.

Systems and methods to prevent system crashes due to link failure in memory mirroring mode

An information handling system includes a processor, a dual in-line memory module (DIMM), and a memory controller coupled to the DIMM. The memory controller provides interrupts to the processor each time a read transaction from the DIMM results in a correctable read error. The processor instantiates a failure predictor to receive the interrupts, accumulate a count of the interrupts, and provide a first error indication when the count exceeds a first error threshold. The failure predictor increments the count each time the predictor receives a particular interrupt and decrements the count in accordance with an error leak rate. The error leak rate has a first value when the DIMM is newer than a first age threshold and has a second value when the DIMM is older than the first age threshold.

System and method to control memory failure handling on double-data rate dual in-line memory modules

An information handling system includes a processor, a dual in-line memory module (DIMM), and a memory controller coupled to the DIMM. The memory controller provides interrupts to the processor each time a read transaction from the DIMM results in a correctable read error. The processor instantiates a failure predictor that receives the interrupts, accumulates a count of the interrupts, and provides an error indication when the count exceeds an error threshold. The failure predictor receives a first in time interrupt, suspends the accumulation of the count for a first duration of time in response to receiving the first in time interrupt, and resumes the accumulation of the count. In resuming the accumulation of the count, the failure predictor increments the count each time the predictor receives a first subsequent interrupt and decrements the count in accordance with an error leak rate.

System and method to control memory failure handling on double-data rate dual in-line memory modules via suspension of the collection of correctable read errors

An information handling system includes a first memory, a second memory, and a central processor. The first memory includes a buffer to store uncorrected no action (UCNA) errors for the second memory. The central processor detects a memory data corruption in the second memory, stores a first UCNA error associated with the memory data corruption in the buffer implemented within the first memory, determines whether the buffer is full, and erases an oldest in time UCNA error from the buffer in response to the buffer being full.

System and method for BIOS to ensure UCNA errors are available for correlation

An information handling system includes a central processing unit, which in turn includes a system memory and a first processor core. The system memory stores Common Platform Error Record (CPER) entries in a queue. The first processor core stores the hardware error in a bank of a machine check bank register of the first processor core, and generates a system management interrupt (SMI) in response to storing the hardware error in the bank. The central processing unit receives the generated SMI, clears CPER entries within the queue of the system memory that are outside a specific timespan before a corrected machine check error indication associated with the generated SMI is received, adds a CPER entry associated with the corrected machine check error indication to the queue of the system memory, and disables SMI generation from the machine check bank number in response to the number of CPER entries exceeding the threshold count.

System and method to correlate corrected machine check error storm events to specific machine check banks

An information handling system (IHS) is disclosed wherein the system includes a processor associated with at least one performance state (P-state), and a memory in communication with the processor. The memory is operable to store a virtualization software and a basic input/out system (BIOS). The BIOS is configured to report a parameter of the P-state to the virtualization software. In addition, the BIOS is configured to transition the processor into a desired P-state. A method for managing performance states in an information handling system (IHS) is further disclosed wherein the method includes providing a basic input/output system (BIOS) in communication with a processor, the processor associated with an at least one performance state (P-state) and reporting a parameter of the at least one P-state to a virtualization software via the BIOS. The method further includes transitioning the processor to a desired P-state via the BIOS.

Methods for managing performance states in an information handling system

A method of predicting failure of an information handling device, such as a server, by monitoring an error rate, i.e., n errors per error period. Errors are reported only if the error rate is exceeded. An error count is kept, and errors are leaked from the count if the time difference between errors is more than the error period.

System and method for predictive failure detection

An apparatus and method are disclosed for reducing the amount of time to execute a boot sequence, such as a power-on self-test (POST) routine, by eliminating a scan for devices interfaced with a local bus associated with a computer system. A detection circuit interfaces with a card slot through the local bus and generates a status bit indicating whether the configuration of devices for the computer system changed after completion of a first boot sequence. A processor interfaces with the local bus and reads the status bit during a second boot sequence. If the status bit indicates that the computer system device configuration remains the same, the processor eliminates the scan for devices interfaced with the computer system.

Apparatus and method for detecting a change in system hardware configuration to reduce the amount of time to execute a post routine

A computer system and a method for allocating power to hot-plugged adapter cards placed in a card slot so as to delay, the power allocation until a user is clear of the adapter card. The computer system conventionally includes a processor, a card slot in data communication with the processor, a memory in data communication with the processor, and a power supply in electrical communication with the processor. The memory stores computer-readable data that includes code to be operated on by the processor to allocate power to the card slot upon both a detection of a change of state of the card slot and the occurrence of a predefined system event. The predefined system event is typically a system interrupt that is generated in response to an activation of a switch in electrical communication with the processor.

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Cedar Park, TX, United States of America

Tuyet-Huong Thi Nguyen