Freescale Semiconductor,inc.

Nxp B.v.

Motorola Corporation

Nxp Usa, Inc.

Tushar Praful Merchant

Ramachandran Muralidhar

Rajesh A Rao

Mark Douglas Hall

Anirban Roy

Chun-Li Liu

Marius K Orlowski

Leo Mathew

Matthew W Stoker

Dharmesh Jawarani

Lakshmanna Vishnubhotla

Gowrishankar L Chindalore

Michael Alan Sadd

Philip J Tobin

Jane A Yater

Varughese Mathew

Rama I Hegde

Asanga H Perera

Christopher C Hobbs

Sam S Garcia

David Gilmer

Hsing H Tseng

Leonard John Borucki

David C Sing

Joe Mogab

Craig Allan Cavins

Maryfe Hernandez

An integrated circuit DAC device and fabrication method are provided with a linear bias ladder circuit which generates a plurality of bias voltages, an inverting operational amplifier configured to generate an analog output voltage in response to an input current signal, and a plurality of MMT devices connected between the linear bias ladder circuit and the inverting operational amplifier to implement a DAC with a first current control gate of each MMT device connected to one of the plurality of N different bias voltages, with a second switch control gate of each MMT device connected to receive one of a plurality digital input code values, with a drain terminal of each MMT device connected to a digital bias voltage (Vdbias), and with a source terminal of each MMT device connected to provide the input current signal to the inverting operational amplifier.

DAC and ADC using MMT devices

A semiconductor device and fabrication method are described for forming a nanosheet transistor device by forming a nanosheet transistor stack (-) of alternating Si and SiGe layers which are selectively processed to form metal-containing current terminal or source/drain regions () and to form control terminal electrodes (A-D) which replace the SiGe layers in the nanosheet transistor stack and are positioned between the Si layers which form transistor channel regions in the nanosheet transistor stack to connect the metal source/drain regions, thereby forming a nanosheet transistor device.

Nanosheet transistors with reduced source/drain resistance and associated method of manufacture

A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (--) which are separated from one another by a barrier oxide layer () and which are separately processed to form first remnant silicon germanium nanosheet layers () in the bottom Si/SiGe superlattice structures having a first gate length dimension (DG) and to form second remnant silicon germanium nanosheet layers () in the top Si/SiGe superlattice structures having a second, smaller gate length dimension (DG) so that the nanosheet transistor stack may then be processed to simultaneously form bottom and top gate electrodes which replace, respectively, the first and second remnant silicon germanium nanosheet layers.

Nanosheet device with different gate lengths in same stack

A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (--) which are separated from one another by a barrier oxide layer () and which are separately processed to form bottom gate electrodes having a first gate structure (A-B) in the bottom Si/SiGe superlattice structures and to form top gate electrodes having a second, different gate structure (A-B) in the top Si/SiGe superlattice structures.

Nanosheet transistors with different gate materials in same stack and method of making

A nanosheet semiconductor device and fabrication method are described for integrating the fabrication of nanosheet transistors () and capacitors/sensors () in a single nanosheet process flow by forming separate transistor and capacitor/sensor stacks (A-A,B-B) which are selectively processed to form gate electrode structures (A-C) which replace remnant SiGe sandwich layers in the transistor stack, to form silicon fixed electrodes using silicon nanosheets (C,C) on a first side of the capacitor/sensor stack, and to form SiGe fixed electrodes using SiGe nanosheets (C,C,C) from the middle of remnant SiGe sandwich layers in the capacitor/sensor stack (e.g.,-) which are separated from the silicon fixed electrodes by selectively removing top and bottom SiGe nanosheets (e.g.,--) from the remnant SiGe sandwich layers in the capacitor/sensor stack.

Method of making nanosheet fringe capacitors or MEMS sensors with dissimilar electrode materials

A nanosheet MEMS sensor device and method are described for integrating the fabrication of nanosheet transistors () and MEMS sensors () in a single nanosheet process flow by forming separate nanosheet transistor and MEMS sensor stacks (A-A,B-B) of alternating Si and SiGe layers which are selectively processed to form gate electrodes (A-C) which replace the silicon germanium layers in the nanosheet transistor stack, to form silicon fixed electrodes using silicon layers (B-B-) on a first side of the MEMS sensor stack, and to form silicon cantilever electrodes using silicon layers (B-B-) on a second side of the MEMS sensor stack by forming a narrow trench opening () in the MEMS sensor stack to expose and remove remnant silicon germanium layers on the second side in the MEMS sensor stack.

Nanosheet MEMs sensor device and method of manufacture

A semiconductor device and fabrication method are described for integrating a nanosheet transistor with a capacitor or nonvolatile memory cell in a single nanosheet process flow by forming a nanosheet transistor stack (-) of alternating Si and SiGe layers which are selectively processed to form epitaxial source/drain regions (A,B) and to form gate electrodes (A-D) which replace the silicon germanium layers in the nanosheet transistor stack, and then selectively forming one or more insulated conductive electrode layers (e.g.,) adjacent to the nanosheet transistor to define a capacitor or nonvolatile memory cell that is integrated with the nanosheet transistor.

Method of making nanosheet local capacitors and nvm devices

A process and device structure is provided for increasing capacitance density of a capacitor structure. A sandwich capacitor is provided in which a bottom silicon-containing conductor plate is formed with holes or cavities, upon which an oxide layer and a top silicon-containing layer conductor is formed. The holes or cavities provide additional capacitive area, thereby increasing capacitance per footprint area of the capacitor structure. The holes can form, for example, a line structure or a waffle-like structure in the bottom conductor plate. Etching techniques used to form the holes in the bottom conductor plate can also result in side wall tapering of the holes, thereby increasing the surface area of the silicon-containing layer defined by the holes. In addition, depth of holes can be adjusted through timed etching to further adjust capacitive area.

Low-leakage, high-capacitance capacitor structures and method of making

A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structrure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.

Phase change memory cell with heater and method therefor

A phase change memory (PCM) cell includes a transistor, a PCM structure, and a heater. The transistor has a first current electrode and a second current electrode in a structure, and a channel region having a first portion along a first sidewall of the structure and having a second portion along a second sidewall of the structure. The second sidewall is opposite the first sidewall. The transistor has a control electrode that has a first portion adjacent to the first sidewall and a second portion adjacent to the second sidewall. The PCM structure exhibits first and second resistive values when in first and second phase states, respectively. The heater is on the structure and produces heat when current flows through the heater for changing the phase state of the phase change structure.

Method of making a phase change memory cell having a silicide heater in conjunction with a FinFET

A method for making a semiconductor device () includes providing an interconnect layer () over an underlying layer (), forming a first insulating layer () over the interconnect layer, and forming an opening () through the insulating layer to the interconnect layer. A first conductive layer () is formed over the interconnect layer and in the opening. This is performed by plating so it is selective. A second conductive layer () in the opening is formed by displacement by immersion. This is performed after the first conductive layer has been formed. The result is the second conductive layer is formed by a selective deposition and is effective for providing it with bridging material. A layer of bridgeable material () is formed over the second conductive layer and in the opening. A third conductive layer () is formed over the bridgeable material. The semiconductor device may be useable as a conductive bridge memory device.

Method of making a semiconductor device including a bridgeable material

A phase change memory cell has a first electrode, a plurality of pillars, and a second electrode. The plurality of pillars are electrically coupled with the first electrode. Each of the pillars comprises a phase change material portion and a heater material portion. The second electrode is electrically coupled to each of the pillars. In some examples, the pillars have a width less than 20 nanometers.

Phase change memory structures

A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.

An electronic device can include a layer of discontinuous storage elements. A dielectric layer overlying the discontinuous storage elements can be substantially hydrogen-free. A process of forming the electronic device can include forming a layer including silicon over the discontinuous storage elements. In one embodiment, the process includes oxidizing at least substantially all of the layer. In another embodiment, the process includes forming the layer using a substantially hydrogen-free silicon precursor material and oxidizing at least substantially all of the layer.

Process of forming an electronic device including a layer of discontinuous storage elements

Embodiments of non-volatile semiconductor devices include a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric, and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.

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Austin, TX, United States of America

Tushar Praful Merchant