Texas Instruments Corporation

Iowa State University Research Foundation Inc

Turker Kuyel

Kumar Lakshmi Parthasarathy

Mark A Burns

Abdullah Yilmaz

Degang James Chen

Randall L Geiger

David Ta-wei Kao

Gabriel Morcan

Le Jin

Turgut Feyiz

Recursive digital filter circuitry which avoids persistent unstable conditions therein provides a serial clock signal, a synchronization signal, and a serial data input to corresponding inputs of a 3-wire serial interface circuit to produce a serial clock output signal, a synchronization output signal, and a parallel data output signal which are applied to corresponding inputs of a recursive digital filter. The serial clock signal and the synchronization signal are input to an auto-reset circuit which detects a fault associated with the synchronization signal or the serial clock signal and produces a reset signal in response to detection of the fault for resetting the recursive digital filter.

Automatic input error recovery circuit and method for recursive digital filters

A string DAC having 2string resistors includes a plurality of switches for selectively coupling, according to the decoding of an M-bit MSB subword, the voltage across a string resistor to an interpolation sub-DAC which interpolates it according to the decoding of an N-bit mid-subword. The voltage across the string resistor is multiplexed, according to the decoding of an N-bit mid-subword, to various inputs of 2differential transistor pairs of an interpolation amplifier. A P-bit delta sigma modulator produces a delta sigma modulated signal, according to a P-bit LSB subword, to control multiplexing of voltages on the terminals of the string resistor to an input of one of the differential transistor pairs selected by decoding of the N-bit mid-subword to monotonically average a contribution of the selected differential transistor pair to generation of an output voltage representing a word including the M-bit, N-bit, and P-bit subwords.

High-speed, high-resolution voltage output digital-to-analog converter and method

A method for testing a circuit includes determining at least one performance characteristic of the circuit based on a functional relationship between excitation signals or on a functional relationship between measurement devices. The method is implemented either as a part of a built-in self test circuit of an integrated circuit or for production testing.

Method for testing analog and mixed-signal circuits using functionally related excitations and functionally related measurements

A system and method of calibrating a digital-to-analog converter (DAC) such as a resistor string DAC that reduces costs by making more efficient use of integrated circuit chip area, without requiring analog calibration circuits. The DAC calibration system includes a main DAC to be calibrated, a memory, and calibration logic circuitry for performing arithmetical operations. The memory stores a predetermined number of digital code values in respective memory locations, which are indexed by corresponding voltage values. The digital code values represent DAC input code values which, when applied to the main DAC, would generate the corresponding index voltage values as DAC output voltage levels. The stored DAC input code values and the corresponding DAC output voltage levels, which are determined using an external tester, define piecewise linear (PWL) breakpoint code values of a PWL approximation of the DAC transfer function.

All-digital calibration of string DAC linearity using area efficient PWL approximation: eliminating hardware search and digital division

A method and apparatus for compensating for offset and drift of offset in an amplifier circuit having metal oxide semiconductor transistors in an input stage thereof and including a node responsive to a bias to change the offset of the amplifier circuit. In one embodiment, an offset digital-to-analog converter provides a first programmable bias corresponding to an offset of the amplifier circuit. A drift digital-to-analog converter provides a second programmable bias corresponding to a drift of the offset of the amplifier circuit. The first programmable bias and the second programmable bias are combined and coupled to the node. In another embodiment, a first programmable offset/drift generator is provided, capable of sourcing a first bias to the amplifier node compensating for a first portion of the offset and a first portion of the drift of the offset of the amplifier circuit. A second programmable offset/drift generator is provided, capable of sourcing a second bias to the amplifier node compensating for a second portion of the offset and a second portion of the drift of the offset of the amplifier circuit, wherein the rate of drift compensation with temperature of the second bias is different from the rate of compensation of the second bias. By suitable programming of the first and second programmable offset/drift generators the compensation of the offset and the offset of the drift of the amplifier circuit may be optimized.

Compensation of offset drift with temperature for operational amplifiers

A system and method of calibrating a digital-to-analog converter (DAC) such as a resistor string DAC that reduces costs by making more efficient use of semiconductor die area. A digital-to-analog converter includes a main DAC to be calibrated, a memory, a plurality of calibration DACs, and an analog summing circuit. The main DAC receives digital input code values, and converts the respective input code values into an analog signal. A first calibration DAC receives a predetermined number of lower order bits of the respective input code values, and interpolates between a positive reference voltage and a negative reference voltage to generate linear waveforms for the PWL approximation. A second calibration DAC generates the positive reference voltage, and a third calibration DAC generates the negative reference voltage. The memory stores a plurality of PWL breakpoint code values representing respective integral non-linearity error values of the main DAC, and applies consecutive PWL breakpoint code values to the second and third calibration DACs, respectively, to generate the positive and negative reference voltages for the first calibration DAC.

All-analog calibration of sting-DAC linearity: application to high voltage processes

A calibrated digital-to-analog converter (DAC) ( &prime;) has a main DAC ( ) having a digital input and an analog output. An on-chip memory ( ) stores measured INL values of the main DAC at a few selected input codes, and digital interpolation ( ) is used to approximate INL error values at all input codes ( ). To cancel the INL errors of the main DAC, outputs of this digital interpolation are sent to a calibration DAC ( ), which has an analog output subtracted from the analog output of the main DAC. This subtraction can also be done in the digital domain, removing the need for a calibration-DAC when a main DAC with higher bit-count is designed.

Piecewise linear calibration method and circuit to correct transfer function errors of digital to analog converters

According to one embodiment of the present invention, a system ( ) for measuring overall jitter is disclosed that includes a data converter ( ) that measures a signal to generate a first measurement set ( ) and a second measurement set ( ), which are used to compute overall jitter. According to one embodiment of the present invention, a method for measuring overall jitter is disclosed. The data converter ( ) generates the first measurement set ( ) and the second measurement set ( ) by measuring the signal. The overall jitter is computed using the measurement sets ( and ). According to one embodiment of the present invention, a system ( ) for measuring internal jitter is disclosed that includes a splitter ( ) that splits a signal into an input signal ( ) and a clock signal ( ). The data converter ( ) measures the input signal ( ) to generate a first data set and a second data set, which are used to compute the internal jitter of the data converter ( ). According to one embodiment of the present invention, a method for measuring internal jitter is disclosed. A signal is split into an input signal ( ) and a clock signal ( ). The data converter ( ) measures the input signal to generate the first data set ( ) and the second data set ( ). The internal jitter is computed using the first data set ( ) and the second data set ( ). The external jitter is computed from the overall and internal jitter. The signal-to-noise ratio of the data converter ( ) is computed from the external jitter.

Method and system for measuring jitter

A system and method for measuring jitter. One class of embodiments is particularly useful for testing the aperture jitter of a high speed Analog to Digital (A/D) converter. Aperture jitter in a Sample and Hold circuit (S/H) or in an A/D converter introduces noise into the sampled signal, which is more extreme in areas of the input waveform that have a steep positive or negative slope. The preferred embodiment allows an easy and inexpensive way to measure aperture jitter in S/H and A/D circuits. The technique can also be adapted for measuring edge jitter in digital clock signals or in analog sine wave signals.

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Austin, TX, United States of America

Turker Kuyel