Taiwan Semiconductor Manufacturing Comp. Ltd.

Tuo-Hung Ho

Liang-Gi Yao

Ming-Fang Wang

Chih-Wei Yang

Chi-Chun Chen

Chih-Chang Chen

Shih-Chang Chen

Yeou-Ming Lin

A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.

Dual-gate structure and method of fabricating integrated circuits having dual-gate structures

A chemical vapor deposition (CVD) method for forming a microelectronic layer within a microelectronic product employs a wetting material treatment of a substrate upon which is formed the microelectronic layer. The wetting material treatment provides for an attenuated incubation or induction time when forming the microelectronic layer, particularly within the context of a digital CVD method, such as an atomic layer CVD method. The microelectronic layer is thus formed with enhanced manufacturability.

Chemical vapor deposition (CVD) method employing wetting pre-treatment

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Chia-Yi, Taiwan

Tuo-Hung Ho