Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

National Taiwan Normal University

Tsinghua University

Novatek Microelectronics Corp.

Tung-Ying Lee

Yu-Chao Lin

Shao-Ming Yu

Meng-Hsuan Hsiao

Carlos H Diaz

Chien-Min Lee

Xinyu Bao

Wei-Sheng Yun

Tzu-Chiang Chen

Hung-Li Chiang

Ling-Yen Yeh

Chun-Chieh Lu

Cheng-Hsien Wu

Kai-Tai Chang

Yuan-Tien Tu

Hengyuan Lee

Yasutoshi Okuno

Pang-Yen Tsai

Tse-An Chen

Winnie Victoria Wei-Ning Chen

Yu-Lien Huang

Chih-Sheng Chang

Chih-Chieh Yeh

Tzu-Chung Wang

Bo-Jiun Lin

Ying-Yu Chen

Shy-Jay Lin

Chao-Ching Cheng

I-Sheng Chen

Cheng-Yi Peng

Win-San Khwa

Miin-Jang Chen

Jung-Piao Chiu

Chen-Feng Hsu

Szu-Wei Huang

Ming-Yuan Song

Huan-Sheng Wei

Cheng-Chun Chang

Yu-Tung Yin

Meng-Chien Yang

Meng-Fan Chang

Lain-Jong Li

Jin-Aun Ng

Chun-Hsiang Fan

Jin Cai

Jen-Chieh Liu

Chi-Kang Liu

Shang-Hong Lai

Yung-Ta Li

Da-Ching Chiou

Yen-Lin Huang

Clement Hsing-Jen Wann

Shin-Wei Shen

Yu-Sheng Chen

Chia-Cheng Ho

Chen-Ping Chen

Ming-Jie Huang

Ming-Shiang Lin

Meng-Ku Chen

Chien-Hsing Lee

Elia Ambrosi

Ming-Feng Chiang

Tzu-Shan Chang

Ming-Hsuan Lin

A control circuit, a memory system and a control method are provided. The control circuit is configured to control a plurality of memory cells of a memory array. The control circuit comprises a program controller. The program is configured to program a first electrical characteristic distribution and a second electrical characteristic distribution of the memory cells according to error tolerance of a first bit of a data type. A first overlapping area between the first electrical characteristic distribution and the second electrical characteristic distribution is smaller than a first predetermined value.

Control circuit, memory system and control method

Provided is a memory cell including a selector disposed over a substrate, a memory element and a connecting pad. The selector includes a bottom electrode, an ovonic threshold switch layer on the bottom electrode, an inter-electrode over the ovonic threshold switch layer, and an intermediate layer between the ovonic threshold switch layer and the inter-electrode. The memory element is disposed on the selector. The connecting pad is disposed on the memory element.

Semiconductor device, memory cell and method of forming the same

Semiconductor devices and methods of manufacturing the same are provided in which memory cells are manufactured with a double sided word line structure. In embodiments a first word line is located on a first side of the memory cells and a second word line is located on a second side of the memory cells opposite the first side.

Semiconductor devices with a double sided word line structure

An ovonic threshold switch (OTS) selector and a memory device including the OTS selector is provided. The OTS selector includes a switching layer formed of a GeCTe compound further doped with one or both of nitrogen and silicon, and exhibits improved thermal stability and electrical performance.

Memory device and manufacturing method thereof

A memory cell includes a bottom electrode, a memory element, spacers, a selector and a top electrode. The memory element is located on the bottom electrode and includes a first conductive layer, a second conductive layer and a storage layer. The first conductive layer is electrically connected to the bottom electrode. The second conductive layer is located on the first conductive layer, wherein a width of the first conductive layer is smaller than a width of the second conductive layer. The storage layer is located in between the first conductive layer and the second conductive layer. The spacers are located aside the second conductive layer and the storage layer. The selector is disposed on the spacers and electrically connected to the memory element. The top electrode is disposed on the selector.

Method of forming semiconductor device

A semiconductor structure includes a substrate and an interconnect. The substrate has a semiconductor device. The interconnect is disposed over the substrate and electrically coupled to the semiconductor device, and includes a metallization layer and a capping layer. The metallization layer is disposed over the substrate and includes a via portion and a line portion connecting to the via portion. The capping layer covers the line portion, where the line portion is sandwiched between the via portion and the capping layer, and the capping layer includes a plurality of sub-layers.

Semiconductor structure and manufacturing methods thereof

A memory device is provided. The memory device includes a bottom electrode, a first data storage layer, a second data storage layer, an interfacial conductive layer and a top electrode. The first data storage layer is disposed on the bottom electrode and in contact with the bottom electrode. The second data storage layer is disposed over the first data storage layer. The interfacial conductive layer is disposed between the first data storage layer and the second data storage layer. The top electrode is disposed over the second data storage layer.

Memory device and operating method thereof

Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.

Methods of writing and forming memory device

A memory device and a semiconductor die are provided. The memory device includes single-level-cells (SLCs) and multi-level-cells (MLCs). Each of the SLCs and the MLCs includes: a phase change layer; and a first electrode, in contact with the phase change layer, and configured to provide joule heat to the phase change layer during a programming operation. The first electrode in each of the MLCs is greater in footprint area as compared to the first electrode in each of the SLCs.

Memory device and semiconductor die having the memory device

A phase-change memory device and a method for fabricating the same are provided. The phase-change memory device comprises a first electrode, a stack and a multi-layered spacer. The first electrode is disposed on and electrically connected to an interconnect wiring of the interconnect structure. The stack is disposed on the first electrode and comprises a phase-change layer disposed on the first electrode and a second electrode disposed on the phase-change layer. The multi-layered spacer covers the stack. A first portion of the multi-layered spacer covers a top surface of the stack, and a second portion of the multi-layered spacer covers a sidewall of the stack.

Phase-change memory device and method for fabricating the same

A device includes a plurality of semiconductor fins extending from a substrate. A plurality of first source/drain regions are epitaxially grown from first regions of the semiconductor fins. Adjacent two of the plurality of first source/drain regions grown from adjacent two of the plurality of semiconductor fins are spaced apart by an isolation dielectric. A gate structure laterally surrounds second regions of the plurality of semiconductor fins above the first regions of the plurality of semiconductor fins. A plurality of second source/drain regions are over third regions of the plurality of semiconductor fins above the second regions of the plurality of semiconductor fins.

Semiconductor device

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate. The gate stack is between the first source/drain structure and the second source/drain structure. The semiconductor device structure includes an inner spacer layer covering a sidewall of the first source/drain structure and partially between the gate stack and the first source/drain structure. The first nanostructure passes through the inner spacer layer. The semiconductor device structure includes a dielectric structure over the gate stack and extending into the inner spacer layer. The dielectric structure covers a top surface, an inner wall, and a lower surface of the inner spacer layer.

Semiconductor device structure with nanostructure

A memory device includes a substrate, a transistor disposed over the substrate, an interconnect structure disposed over and electrically connected to the transistor, and a memory stack disposed between two adjacent metallization layers of the interconnect structure. The memory stack includes a bottom electrode disposed over the substrate and electrically connected to a bit line, a memory layer disposed over the bottom electrode, a selector layer disposed over the memory layer, and a top electrode disposed over the selector layer and electrically connected to a word line. Besides, at least one moisture-resistant layer is provided adjacent to and in physical contact with the selector layer, and the at least one moisture-resistant layer includes an amorphous material.

Memory devices and methods of forming the same

Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, a top electrode, and a storage element layer. The storage element layer is disposed between the bottom and top electrodes. An extending direction of a sidewall of the storage element layer is different from an extending direction of a sidewall of the top electrode. A semiconductor device having the memory cell is also provided.

Memory cell, method of forming the same, and semiconductor device having the same

A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.

Semiconductor device with fin end spacer dummy gate and method of manufacturing the same

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Hsinchu, Taiwan

Tung-Ying Lee