Winbond Electronics Corporation

Other

Windbond Electronics Corp.

Winbond Electronics Corporation America

Tung-Yi Chan

Dah-Bin Kao

Loc Bao Hoang

Albert T Wu

Albert M Wu

Hsin-Hung Chou

Chia Hua Ho

Meng-Chang Chan

Yu-Cheng Chiao

Chen-Hsi Lin

Wen-Ying Wen

A method for fabricating a stacked electronic device is provided. A first three-dimensional (3D) printing is performed to form a first insulating layer and a plurality of first redistribution layers (RDLs) on a first substrate. A second 3D printing is performed to form a second substrate and a plurality of through-substrate vias (TSVs) on the first insulating layer, in which the plurality of TSVs is electrically connected to the plurality of first RDLs. A third 3D printing is performed to form a second insulating layer and a plurality of second RDLs on the second substrate, in which the plurality of second RDLs is electrically connected to the plurality of TSVs. A plurality of contacts of a third substrate is bonded to the plurality of second RDLs, so that the substrate is mounted onto the second insulating layer. The disclosure also provides a stacked electronic device formed by such a method.

Stacked electronic device and method for fabricating the same

A method for fabricating a stacked package device is provided. A second substrate is adhered onto a first substrate. The first substrate includes a plurality of first bonding pads, and the second substrate includes a plurality of second bonding pads. A three-dimensional (3D) printing is performed to form an encapsulating layer covering the first substrate and the second substrate and to form a plurality of bonding wires in the encapsulating layer. Each bonding wire includes a first portion connected to one of the plurality of first bonding pads. The disclosure also provides a stacked package device formed by such a method.

Stacked package device and method for fabricating the same

A transistor structure having a dedicated erase gate where the transistor can be used as a memory cell is disclosed. The presently preferred embodiment of the transistor comprises a floating gate disposed on a substrate and having a control gate and an erase gate overlapping said floating gate, with drain and source regions doped on the substrate. By providing a dedicated erase gate, the gate oxide underneath the control gate can be made thinner and can have a thickness that is conducive to the scaling of the transistor. The overall cell size of the transistor remains the same and the program and read operation can remain the same. Both the common source and buried bitline architecture can be used, namely twin well or triple well architectures. A memory circuit using the transistors of the present invention is disclosed as well for flash memory circuit applications.

Method and apparatus for split gate source side injection flash memory cell and array with dedicated erase gates

A semiconductor memory array and methods therefor is provided herein comprising a substrate; a plurality of memory cell field effect transistors formed on said substrate and being arranged thereon into rows and columns of transistors, each transistor includes a channel region interposed between drain and source regions, and overlaid by a control gate region; a plurality of first diffused elongated regions formed within said substrate that electrically connect in common the drain regions of transistors in respective columns; a plurality of second diffused elongated region formed within said substrate that electrically connect in common the source regions of transistors in respective columns; and a plurality of elongated conductive line formed over said substrate that electrically connect in common the control gate regions of transistors in respective rows.

Semiconductor memory array with buried drain lines and processing methods therefor

A method is disclosed for creating a sub-minimum opening in a semiconductor device, comprising the steps of: a) providing a first layer; b) providing a second layer over said first layer; c) providing a third layer over said second layer; d) providing a photoresist mask over said third layer; e) etching said third layer to form defined structures; f) depositing a fourth layer for forming spacers; g) etching said fourth layer to form said spacers; and h) etching said first layer to form an opening in said first layer. In etching the fourth layer to form the spacers, the third layer is generally etched away to form an opening to the first layer, and, in the following step, an opening (or feature) can be etched on the first layer. Generally speaking, the first and third layers can be of any material and should have similar etching rate; the second and fourth layers can be of any material and should have similar etching rate. However, the material for the first and third layers versus the material for the second and fourth layers should have highly dissimilar etching rates. Materials for these layers include and are not limited to polysilicon, oxide, nitride, and metal.

Method for forming minute openings in semiconductor devices

A semiconductor memory array and methods therefor is provided herein comprising a substrate; a plurality of memory cell field effect transistors formed on said substrate and being arranged thereon into rows and columns of transistors, each transistor includes a channel region interposed between drain and source regions, and overlaid by a control gate region; a plurality of first diffused elongated regions formed within said substrate that electrically connect in common the drain regions of transistors in respective columns; a plurality of second diffused elongated regions formed within said substrate that electrically connect in common the source regions of transistors in respective columns; and a plurality of elongated conductive line formed over said substrate that electrically connect in common the control gate regions of transistors in respective rows.

Semiconductor memory array with buried drain lines and methods therefor

An analog memory device includes a memory cell transistor and a memory follower transistor that share a common floating gate. The drain of the memory cell transistor is coupled to a first voltage source. The control gate of the memory cell transistor is coupled to a second voltage source. A programming transistor is coupled between the source of the memory cell transistor and a reference voltage. A comparator receives a first input analog signal to be stored in the memory cell transistor and is coupled to the memory follower transistor to receive the signal held on the floating gate. The output of the comparator is coupled to the control gate of the programming transistor to selectively turn it on to store the analog signal in the memory cell transistor.

Memory device and method of operation

A method for manufacturing a semiconductor memory cell with a floating gate having a predetermined length includes the steps of: growing a thin oxide layer over a substrate; depositing a polysilicon layer over the thin oxide layer; depositing a silicon nitride layer over the polysilicon layer; masking and etching the nitride layer down to the polysilicon layer so as to form an oxide receiving groove in the nitride layer, the groove being parallel to a longitudinal axis of the floating gate to be formed and being longer than the predetermined width of the floating gate to be formed, and the width of the receiving groove in latitudal axis is equal to the predetermined length of the floating gate, the receiving groove overlapping a floating gate region to be defined on the polysilicon layer; growing a polysilicon oxide layer in the receiving groove; removing the nitride layer; providing a mask which is transverse to the polysilicon oxide layer and which has a width equal to the predetermined length of the floating gate to be formed, the mask covering a portion of the polysilicon oxide layer which is directly above the floating gate region; etching remaining portion of the polysilicon oxide layer not covered by the mask; removing the mask; and etching the polysilicon layer with the portion of the polysilicon oxide layer serving as a mask so as to form the floating gate.

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Taichung, Taiwan

Tung-Yi Chan